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1
Copyright © Cirrus Logic, Inc. 2005
(All Rights Reserved)
http://www.cirrus.com
CS5529
16-bit, Programmable ∆Σ ADC with 6-bit Latch
Features
z Delta-sigma Analog-to-digital Converter
- Linearity Error: 0.0015%FS
- Noise-free Resolution: 16-Bits
z 2.5 V Bipolar/Unipolar Buffered Input Range
z 6-bit Output Latch
z Eight Digital Filters
- Selectable Output Word Rates
- Output Settles in One Conversion Cycle
- 50/60 Hz ±3 Hz Simultaneous Rejection
z Simple Three-wire Serial Interface
- SPI™ and Microwire™ Compatible
- Schmitt Trigger on Serial Clock (SCLK)
z System/Self-calibration with R/W Registers
z Power Supply Configurations
- VA+ = +5 V; VA- = 0 V; VD+ = +3 V to +5 V
- VA+ = +2.5 V; VA- = -2.5 V; VD+ = +3 V to +5 V
- VA+ = +3.0 V; VA- = -3.0 V; VD+ = +3.0 V
z Low Power Consumption: 2.6 mW
General Description
The 16-bit CS5529 is a low-power, programmable ∆Σ
ADC (Analog-to-Digital Converter), which includes
coarse/fine charge buffers, a fourth-order ∆Σ modulator,
a calibration microcontroller, a digital filter with program-
mable decimation rates, a 6-bit output latch, and a three-
wire serial interface. The ADC is designed to operate
from single or dual analog supplies and a single digital
supply.
The digital filter is programmable with output update
rates between 1.88 Hz to 101 Sps. These output rates
are specified for XIN = 32.768 kHz. Output word rates
can be increased by approximately 3X by using XIN =
100 kHz. The filter is designed to settle to full accuracy
for the selected output word rate in one conversion.
When operated at word rates of 15 Sps or less, the filter
rejects both 50 Hz and 60 Hz simultaneously.
Low power, single conversion settling time, programma-
ble output rates, and the ability to handle negative input
signals make this single- or dual-supply product an ideal
solution for isolated and non-isolated applications.
ORDERING INFORMATION
See page 29.
VA+
AIN+
AIN-
VREF+
VREF-
Latch
A0 A1 D0 D1 D2 D3
Calibration
Memory
Calibration µC
Clock
Gen.
XIN XOUT
VA- DGND
1X
1X
Differential
4th Order
Delta-Sigma
Modulator
Digital Filter
Calibration
Register
Control
Register
Output
Register
VD+
CS
SCLK
SDI
SDO
AUG ‘05
DS246F5
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Inhaltsverzeichnis

Seite 1 - General Description

1Copyright © Cirrus Logic, Inc. 2005(All Rights Reserved)http://www.cirrus.comCS552916-bit, Programmable ∆Σ ADC with 6-bit LatchFeaturesz Delta-sigma

Seite 2 - TABLE OF CONTENTS

CS552910 DS246F5GENERAL DESCRIPTIONThe CS5529 is a 16-bit ∆Σ Analog-to-Digital Con-verter (ADC) which includes coarse/fine chargebuffers, a fourth ord

Seite 3 - LIST OF FIGURES

CS5529DS246F5 11ages. The differential voltage between VREF+ andVREF- sets the nominal full scale input span of theconverter. For a single-ended refer

Seite 4 - ANALOG CHARACTERISTICS (T

CS552912 DS246F5Command Register DescriptionsPerform Single ConversionThis command instructs the ADC to perform a single conversion.Perform Continuous

Seite 5

CS5529DS246F5 13SYNC1Part of the serial port re-initialization sequence (see text for use of command).SYNC0End of the serial port re-initialization se

Seite 6 - DYNAMIC CHARACTERISTICS

CS552914 DS246F5Command Time8 SCLKsData Time 24 SCLKs(or 72 SCLKs for Set-up Registers)Write CycleCSSCLKSDIMSBLSBCommand Time8 SCLKsCSSCLKSDIData Time

Seite 7

CS5529DS246F5 15Serial Port InitializationThe serial port is initialized to the command modewhenever a power-on reset is performed or whenthe port ini

Seite 8 - SWITCHING CHARACTERISTICS (T

CS552916 DS246F5running. This allows the converter to quickly returnto the normal or low power mode once the PS/R bitis set back to a logic 0. If D4 i

Seite 9 - DS246F5 9

CS5529DS246F5 17Port FlagThe port flag bit in the configuration register allowsthe user to select the mode in which conversionswill be presented to th

Seite 10 - Voltage Reference Input Model

CS552918 DS246F5Gain Register The gain register span is from 0 to (4-2-22). After Reset the (MSB-1) bit is ‘1’, all other bits are ‘0’.The gain calibr

Seite 11 - Serial Port

CS5529DS246F5 19tions). If a system gain calibration is performed, thecalibrated input must not cause the resulting gainregister’s content, decoded in

Seite 12 - Command Register Descriptions

CS55292 DS246F5TABLE OF CONTENTSCHARACTERISTICS & SPECIFICATIONS ... 4ANALOG CHARACTERISTICS

Seite 13 - Serial Port Interface

CS552920 DS246F5Configuration Register Descriptions D23(MSB) D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12A1 A0 D3 D2 D1 D0 NU LPM WR2 WR1 WR0 U/BD11

Seite 14 - 14 DS246F5

CS5529DS246F5 21Performing ConversionsThe CS5529 offers two modes of performing con-versions: single conversion and continuous conver-sions. The secti

Seite 15 - Power Consumption

CS552922 DS246F5SDO flag falls. For instance, the user can just readthe conversion data register again to exit the contin-uous conversion mode.Note: 1

Seite 16 - Reset System

CS5529DS246F5 23Power Supply ArrangementsThe CS5529 is designed to operate from single ordual analog supplies and a single digital supply.The followin

Seite 17 - Calibration Registers

CS552924 DS246F5analog supplies and a +3 V to +5 V digital supplyto measure ground referenced bipolar signals. Fig-ure 12 illustrates the CS5529 conne

Seite 18 - System Calibration

CS5529DS246F5 25Getting StartedThe CS5529 has many features. From a softwareprogrammer’s perspective, what should be donefirst? To begin, a 32.768 kHz

Seite 19 - Calibration Tips

CS552926 DS246F5PIN DESCRIPTIONSClock GeneratorXIN; XOUT - Crystal In; Crystal Out, Pins 10, 11.A gate inside the chip is connected to these pins and

Seite 20 - Gain -- System Calibration

CS5529DS246F5 27A0, A1 - Logic Outputs (Analog), Pin 5, 6.The logic states of A0-A1 mimic the states of the D22-D23 bits of the configuration register

Seite 21 - Continuous Conversions

CS552928 DS246F5SPECIFICATION DEFINITIONSLinearity ErrorThe deviation of a code from a straight line which connects the two end points of the A/DConve

Seite 22 - Output Coding

CS5529DS246F5 29ORDERING INFORMATIONENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION * MSL (Moisture Sensitivity Level) as specified by IPC/JE

Seite 23 - Power Supply Arrangements

CS5529DS246F5 3LIST OF FIGURESInput models for AIN+ and AIN- pins... 11Input model for VREF+ and

Seite 24 - 24 DS246F5

CS552930 DS246F5PACKAGE DIMENSIONS INCHES MILLIMETERSDIM MIN MAX MIN MAXA 0.000 0.210 0.00 5.33A1 0.015 0.025 0.38 0.64A2 0.115 0.195 2.92 4.95b 0.014

Seite 25 - PCB Layout

CS5529DS246F5 31Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measur

Seite 26 - PIN DESCRIPTIONS

CS55294 DS246F5CHARACTERISTICS & SPECIFICATIONSANALOG CHARACTERISTICS (TA = 25 °C; VA± = ±2.5 V ±5%, VD+ = 5 V ±5%, VREF+ = 2.5 V, VREF- = 0.0 V,

Seite 27 - DS246F5 27

CS5529DS246F5 5ANALOG CHARACTERISTICS (Continued)Notes: 7. See the section of the data sheet which discusses Analog Input Models.8. The minimum Full S

Seite 28 - SPECIFICATION DEFINITIONS

CS55296 DS246F55V DIGITAL CHARACTERISTICS (TA = 25 °C; VA± = ±2.5V ±5%, VD+ = 5V ± 5%.)(See Notes 2 and 11.)Notes: 11. All measurements performed und

Seite 29 - ORDERING INFORMATION

CS5529DS246F5 7ABSOLUTE MAXIMUM RATINGS (DGND = 0 V) (See Note 13.)Notes: 13. All voltages with respect to ground.14. VA+ and VA- must satisfy {(VA+)

Seite 30 - PACKAGE DIMENSIONS

CS55298 DS246F5SWITCHING CHARACTERISTICS (TA = 2 5 ° C ; V A ± = ± 2. 5 V ± 5% , V D+ = 3 V ±5 % or 5 V ±5 % ; In

Seite 31 - 20L SSOP PACKAGE DRAWING

CS5529DS246F5 9Continuous Running SCLK Timing (Not to Scale)CSSCLKt3t6t2t1SDI Write Timing (Not to Scale)CSSCLKMSBMSB-1LSBSDIt3t6t4 t5 t1t2SDO Read Ti

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