Cirrus-logic CS4202 Bedienungsanleitung Seite 17
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CS4202
DS549PP2 17
3.1.3 Command Data Port (Slot 2)
WD[15:0] Write Data. The WD[15:0] bits contain the 16-bit value to be written to the register. If an ac-
cess is a read, this slot is ignored.
NOTE: For any write to an AC ’97 register, the write is defined to be an ‘atomic’ access. This means
that when the Slot 1 Valid bit in output Slot 0 is ‘set’, the Slot 2 Valid bit in output Slot 0 should
always be ‘set’ during the same audio frame. No write access may be split across 2 frames.
3.1.4 PCM Playback Data (Slots 3-4,6-11)
PD[19:0] Playback Data. The PD[19:0] bits contain the 20-bit PCM (2’s complement) playback data for
the left and right DACs, serial data ports, and/or the S/PDIF transmitter. Table 8 on page 30
lists a cross reference for each function and its respective slot. The mapping of a given slot
to the DAC, serial data port, or S/PDIF transmitter is determined by the state of the DSA[1:0]
bits in the Extended Audio ID Register (Index 28h) and the SPSA[1:0] bits in the Extended
Audio Status/Control Register (Index 2Ah).
3.1.5 GPIO Pin Control (Slot12)
GPIO[4:0] GPIO Pin Control. The GPIO[4:0] bits control the CS4202 GPIO pins configured as outputs.
Write accesses using GPIO pin control bits configured as outputs will be reflected on the
GPIO pin output on the next AC-link frame. Write accesses using GPIO pin control bits con-
figured as inputs will have no effect and are ignored. If the GPOC bit in the Misc. Crystal Con-
trol Register (Index 60h) is ‘set’, the bits in output Slot 12 are ignored and GPIO pins
configured as outputs are controlled through the GPIO Pin Status Register (Index 54h).
Bit 191817161514131211109876543210
WD15 WD14 WD13 WD12 WD11 WD10 WD9 WD8 WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0 Reserved
Bit 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD19 PD18 PD17 PD16 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
Bit 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Not Implemented GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 Reserved
- Features 1
- Description 1
- TABLE OF CONTENTS 2
- LIST OF FIGURES 4
- LIST OF TABLES 5
- MIXER CHARACTERISTICS 7
- 9
- 10 DS549PP2 10
- Figure 1. Power Up Timing 10
- Figure 3. Clocks 10
- DS549PP2 11 11
- Figure 6. Test Mode 11
- 2. GENERAL DESCRIPTION 12
- 2.1 AC-Link 12
- 2.2 Control Registers 13
- 2.3 Sample Rate Converters 13
- 2.4 Mixers 13
- 2.5 Input Mux 13
- 2.6 Volume Control 13
- 14 DS549PP2 14
- 3. AC-LINK FRAME DEFINITION 15
- 20 DS549PP2 20
- 4. REGISTER INTERFACE 21
- 0000000ID8ID700ID40000 22
- Mute 0 ML5 22
- 00000SL2SL1SL000000SR2SR1SR0 26
- 000000MIXMSLPBK0000000 28
- 11111111111GP4GP3GP2GP1GP0 35
- 00000000000GS4GS3GS2GS1GS0 35
- 5. SERIAL DATA PORTS 42
- 5.1 Overview 42
- 5.2 Multi-Channel Expansion 42
- 5.3 Serial Data Formats 43
- 6. SONY/PHILIPS DIGITAL 44
- INTERFACE (S/PDIF) 44
- 7. EXCLUSIVE FUNCTIONS 44
- DS549PP2 45 45
- 8.2 Powerdown Controls 46
- + DVdd/Rload/2 47
- 9. CLOCKING 48
- 9.3 Secondary Codec Operation 48
- 22 pF 22 pF 49
- 24.576 MHz 49
- 50 DS549PP2 50
- Figure 19. Differential 1 V 50
- CD Input 50
- 10.1.4 PC Beep Input 51
- 10.1.5 Phone Input 51
- 10.2 Analog Outputs 51
- 10.2.1 Stereo Outputs 51
- 10.2.2 Mono Output 52
- 10.4 Power Supplies 52
- 10.5 Reference Design 53
- 11. GROUNDING AND LAYOUT 54
- DS549PP2 55 55
- CS4202 48-pin 56
- Package Layout 56
- Audio I/O Pins 57
- AC-Link Pins 59
- Clock and Configuration Pins 60
- Misc. Digital Interface Pins 60
- Power Supply Pins 61
- 14.REFERENCE DESIGN 64
- 15.REFERENCES 65
- 48L LQFP PACKAGE DRAWING 66
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