Cirrus-logic EDB9302A Bedienungsanleitung Seite 12
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EDB9302A
Technical Reference Manual
12 ©Copyright 2006 Cirrus Logic, Inc. DS653DB1
Page 9
The two connectors provide a daughter card interface for making custom circuits. J4 is the Memory
Expansion connector and J5 is the Peripheral Expansion connector.
The entire memory bus is connected to J5. It is recommended that the bus signals be buffered if adding
additional memory. However if a CPLD or FPGA is attached there is no reason to buffer. Use proper
engineering practices when using the high-speed memory bus with daughter cards.
The Peripheral Expansion bus has the signals for features not implemented on the EDB9302A board and
for commonly used signals.
Page 10
An external USB 2.0 High-speed Peripheral device is provided. The USB device allows a Host to see the
board as a Mass Storage device. The USB interface chip is connected to the lower 16-bits of the
memory bus.
Page 11
Audio is supported by a Cirrus Logic CS4271 device. Two-channel audio out and line-level audio in is
supported. The audio device communicates to the EP9302 through the I
2
S interface and audio clocks
are generated by the EP9302. The audio in is line level, it is not a microphone-level input. Like the serial
EEPROM, the CS4271 is controlled by the SPI frame signal and EGPIO6. EGPIO6 must be low in order
to communicate to the CS4271 device. As mentioned before, only one SPI™ device can be enabled at a
time.
Page 12
Power and reset circuits are shown on this page. Most of the changes made to this revision of the
EDB9302A board were made in this section. The most important change made is that the board is now
powered from a +12V power supply.
The board has two connectors for input power. J10 is the standard power connector and is where the
power supply provided in the kit attaches. However, a 3x1 header, J11 is also available to supply power
to the board.
The 3.3V power rail is generated from a 3A, adjustable, switching regulator, U27. The 5V power rail is
generated from an identical 3A switching regulator, U28. The 5V supply requires a diode, D7. The 3.3V
supply does not require this diode.
The 1.8V power rail is generated from an 800mA linear regulator. Both the 3.3V and 1.8V power rails are
are monitored by U22 and it will issue a reset if either supply falls below the threshold voltage.
The reset pushbutton can connect directly to the voltage monitor reset input or to a supplementary reset-
detect circuit. Refer to AN258 for more information. This circuit is implemented by U24 and some passive
devices. In general, this circuit is not required with EP9302 Rev E2 devices and may be removed if
desired. It is installed by default. If removed, R109 needs to be installed if the use of the reset pushbutton
is desired.
- EDB9302A 1
- CORPORATE HEADQUARTERS 2
- INTERNATIONAL OFFICES 2
- Table of Contents 3
- List of Figures 4
- 1. EDB9302A Kit Contents 5
- Figure 2. EDB9302A Top View 7
- 3. Getting Started 8
- Figure 3. Block Diagram 9
- 4.1 Circuit Operation 10
- Technical Reference Manual 11
- 5. Software 13
- 6. Developer’s User Forum 14
- 7. Other Useful Information 15
- Appendix A. Schematics 16
- Downloading Files 30
- Windows PC Ethernet Setup 30
- HyperTerminal Setup 33
- Board Programming Setup 34
- Revision History 39
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