Cirrus-logic AN253 Bedienungsanleitung

1Copyright Cirrus Logic, Inc. 2004(All Rights Reserved)http://www.cirrus.comAN253Optimizing Code Speed for the MaverickCrunch™ CoprocessorBrett Davi

AN25310Figure 3: IIR Optimization Example To accomplish this optimization (see Figure 3): 1.) Use the additional registers in the MaverickCrunch co

AN25311variables have been interleaved with data dependant instructions in order to reduce their respective stallpenalties.5. SummaryThe optimization

AN25312Revision Date Changes1 23 January 2004 Initial ReleaseContacting Cirrus Logic SupportFor all product questions and inquiries contact a Cirrus L

AN2532- Conversion between floating point and integer data representations- Sixteen (16) 64-bit general-purpose registers- Four (4) 72-bit accumulator

AN2533Table 2. MaverickCrunch Data Manipulation MnemonicsTable 3. MaverickCrunch Arithmetic Mnemonics2.3 ArchitectureThe MaverickCrunch coprocessor us

AN2534Figure 1. MaverickCrunch Pipelines3. Code Optimization for MaverickCrunchThis section describes guidelines for writing optimized code for the Ma

AN2535Although not a loop optimization technique, Common Sub-Expression Elimination is a speed optimiza-tion technique that can be used in the case wh

AN2536Avoid single or double floating-point division. These operations are not implemented in the Maverick-Crunch and will be carried out by a soft-fl

AN2537fmuls c3, c1, c2<Independent ARM/MaverickCrunch Instruction><Independent ARM/MaverickCrunch Instruction><Independent ARM/Maverick

AN25384. ExamplesThis example illustrates the process of optimizing code for the MaverickCrunch coprocessor at the archi-tecture level. The following

AN2539in a 2-cycle increase in performance per iteration of the loop construct. This increase in performance canbe significant for FIR filters with la