Cirrus-logic CS61584A Bedienungsanleitung

Preliminary Product InformationThis document contains information for a new product.Cirrus Logic reserves the right to modify this product without not

CS61584A10 DS261PP5DS261PP5SWITCHING CHARACTERISTICS - SERIAL PORT (TA = -40 to 85 °C; DV+, TV+, RV+ = nominal ± 0.3 V; Inputs: Logic 0 = 0 V, Logic

CS61584ADS261PP5 11DS261PP5SWITCHING CHARACTERISTICS - PARALLEL PORT (TA = -40 to 85 °C;TV+, RV+ = nominal ± 0.3 V; Inputs: Logic 0 = 0 V, Logic 1 =

CS61584A12 DS261PP5DS261PP5 PWashtasdtasedPWehtcyctrwstrwhtasltddrtdhrtahltahltasltcstdswtdhwtchASDSR/WAD0-AD7(READ)CSAD0-AD7(WRITE)DTACK(READ

CS61584ADS261PP5 13DS261PP5PWashtasdtasedPWehtcyctrwstrwhtasltddrtdhrtahltahltasltcsrtdswtdhwtchASDSR/WAD0-AD7(READ)CSAD0-AD7(WRITE)DTACK (READ and W

CS61584A14 DS261PP5DS261PP5SWITCHING CHARACTERISTICS - JTAG (TA = -40 to 85 °C; TV+, RV+ = nominal ± 0.3 V; Inputs: Logic 0 = 0 V, Logic 1 = RV+)Para

CS61584ADS261PP5 15DS261PP52. OVERVIEWThe CS61584A is a dual line interface for T1/E1applications, designed for high-volume cardswhere low power and h

CS61584A16 DS261PP5DS261PP5The line receiver contains all the necessary clockand data recovery circuits.The jitter attenuator meets AT&T 62411 req

CS61584ADS261PP5 17DS261PP55001.00.50-0.50 250 750 1000NORMALIZEDAMPLITUDEANSI T1.102SPECIFICATIONCS61584AOUTPUTPULSE SHAPETIME (nanoseconds)Figure 1

CS61584A18 DS261PP5DS261PP5The transmitter impedance changes with the linelength options in order to match the load imped-ance (75 Ω for E1 coax, 100

CS61584ADS261PP5 19DS261PP5the CLKE pin determines the clock polarity wherethe output data is stable and valid as shown inTable 2. During Host mode op

CS61584A2 DS261PP5DS261PP5TABLE OF CONTENTS1. CHARACTERISTICS AND SPECIFICATIONS ...

CS61584A20 DS261PP5DS261PP56. REFERENCE CLOCKThe CS61584A requires a reference clock with aminimum accuracy of ±100 ppm for T1 and E1 ap-plications. T

CS61584ADS261PP5 21DS261PP58.3 Bipolar Violation DetectionDuring Host mode operation, a bipolar violation(BPV) is detected by the receiver and reporte

CS61584A22 DS261PP5DS261PP5response to a Loss of Signal condition for eitherchannel is activated by setting bit 1 of the channel1 Mask register to 1.8

CS61584ADS261PP5 23DS261PP5state. LOS will go high, and the status register willbe reset, but the Control, Mask, and ArbitraryWaveform registers remai

CS61584A24 DS261PP5DS261PP5Latched-LOS: Set high on the rising edge of theloss of signal condition. Reading the Status registerclears the Latched-LOS

CS61584ADS261PP5 25DS261PP5Latched-AIS: Set high on the rising edge of thealarm indication signal condition. Reading the Sta-tus register clears the L

CS61584A26 DS261PP5DS261PP5AAO: The Automatic All-Ones (AAO) bit in theMask Register (Channel 1, bit 1) causes an un-framed all-ones pattern to be out

CS61584ADS261PP5 27DS261PP5Factory Test: Must be cleared for normal deviceoperation.9.1.4 Control B RegistersThe Control B registers are read-write re

CS61584A28 DS261PP5DS261PP5sate for waveform degradation that may result fromnon-standard cables, transformers, or protectioncircuitry.Arbitrary wavef

CS61584ADS261PP5 29DS261PP5tude information written for phases 13 and 14 ofeach UI is ignored. Examples of arbitrary wave-forms are illustrated in Fig

CS61584ADS261PP5 3DS261PP59.1.2 Mask Registers ... 25

CS61584A30 DS261PP5DS261PP59.2 Serial Port OperationSerial port operation in Host mode is selected whenthe MODE pin is set high and the P/S pin is set

CS61584ADS261PP5 31DS261PP59.3 Parallel Port OperationParallel port operation in Host mode is selectedwhen the MODE and P/S pins are set high. In this

CS61584A32 DS261PP5DS261PP510.1 JTAG Data Registers (DR)The test data registers are the Boundary-Scan Reg-ister (BSR), the Device Identification Regis

CS61584ADS261PP5 33DS261PP5Bypass Register: The Bypass register consists of asingle bit, and provides a serial path between J-TDIand J-TDO, bypassing

CS61584A34 DS261PP5DS261PP510.5 Run-Test/Idle StateThis is a controller state between scan operations.Once in this state, the controller remains in th

CS61584ADS261PP5 35DS261PP510.10 Pause-DR StateThe pause state allows the test controller to tempo-rarily halt the shifting of data through the test d

CS61584A36 DS261PP5DS261PP510.16 Exit1-IR StateThis is a temporary state. While in this state, if J-TMS is held high, a rising edge applied to J-TCKca

CS61584ADS261PP5 37DS261PP5TCKTMSController stateTDIIR shift-registerParallel output of IRParallel Input to TDRTDR shift-registerParallel output of TD

CS61584A38 DS261PP5DS261PP5TCKTMSController stateTDIParallel Input to IRIR shift-registerParallel output of IRParallel Input to TDRTDR shift-registerR

CS61584ADS261PP5 39DS261PP511.PIN DESCRIPTIONSPower SuppliesAGND - Analog Ground (PLCC pin 33; TQFP pin 23)Analog supply ground pin.AV+ - Analog Power

CS61584A4 DS261PP5DS261PP5Table 13. CS61584A External Components...

CS61584A40 DS261PP5DS261PP5RGND1, RGND2 - Receiver Ground (PLCC pins 30, 39; TQFP pins 20, 29)Power supply ground pins for the receiver circuitry.RV+1

CS61584ADS261PP5 41DS261PP5T1/E1 Data Inputs and OutputsRCLK1, RCLK2 - Receive Clock (PLCC pins 10, 59; TQFP pins 1, 48)RPOS1, RPOS2 - Receive Positiv

CS61584A42 DS261PP5DS261PP5REFCLK - External Reference Clock Input (PLCC pin 36; TQFP pin 26)Input reference clock for the receive and jitter attenuat

CS61584ADS261PP5 43DS261PP5PD1, PD2 - Power Down [Hardware mode] (PLCC pins 24, 45; TQFP pins 15, 34)Setting PD high places the channel in a low power

CS61584A44 DS261PP5DS261PP5INT - Receive Alarm Interrupt [Host mode] (PLCC pin 7; TQFP pin 63)An interrupt is generated to flag the host processor whe

CS61584ADS261PP5 45DS261PP5StatusAIS1, AIS2 - Alarm Indication Signal [Host mode] (PLCC pins 15, 54; TQFP pins 6, 43)The AIS indication goes high when

CS61584A46 DS261PP5DS261PP512.PACKAGE DIMENSIONS INCHES MILLIMETERSDIM MIN NOM MAX MIN NOM MAXA --- 0.55 0.063 --- 1.40 1.60A1 0.002 0.004 0.006 0.05

CS61584ADS261PP5 47DS261PP5 68L PLCC PACKAGE DRAWINGD1DE1 ED2/E2BeA1AINCHES MILLIMETERSDIM MIN NOM MAX MIN NOM MAXA 0.165 0.1825 0.200 4.191 4.6355 5.

CS61584A48 DS261PP5DS261PP513.APPLICATIONS13.1 Line InterfaceFigures 27-29 illustrate typical connection diagramfor T1 and E1 line interface circuits

CS61584ADS261PP5 49DS261PP5AV+ AGND BGREF TV+1 TGND1 RV+1 RGND1 DV+ DGND1:30.01 µFTCLK1TPOS1 (TDATA1)TNEG1 (AIS1)RCLK1 RPOS1 (RDATA1)RNEG1 (BPV1)TCLK2

CS61584ADS261PP5 5DS261PP51. CHARACTERISTICS AND SPECIFICATIONSABSOLUTE MAXIMUM RATINGS Notes: 1. Referenced to RGND1, RGND2, TGND1, TGND2, AGND, DGND

CS61584A50 DS261PP5DS261PP513.2 Power SupplyAs shown in Figure 27, the CS61584A operatesfrom a 3.3 Volt or 5.0 Volt supply. Separate powerand ground p

CS61584ADS261PP5 51DS261PP513.5 TransformersRecommended transformer specifications areshown in Table 17. Based on these specifications,the transformer

CS61584A52 DS261PP5DS261PP5Turns Ratio Manufacturer Part Number Package Type1:2(-IL3 and -IQ3)Halo TD08-1205A 1.5 kV through-hole, singleTG26-1205N1 2

CS61584ADS261F1 53ORDERING INFORMATION ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION* MSL (Moisture Sensitivity Level) as specified by IPC/

CS61584A54 DS261F1REVISION HISTORY Revision Date ChangesPP5 JAN 2001 Preliminary ReleaseF1 SEP 2005 Updated device ordering info. Updated legal notice

CS61584A6 DS261PP5DS261PP5ANALOG CHARACTERISTICS (TA = -40 to 85 °C; power supply pins within ±5% of nominal.)Notes: 7. For input amplitude of 1.2 Vpk

CS61584ADS261PP5 7DS261PP5ANALOG CHARACTERISTICS (Continued)Notes: 16. Using a transformer that meets the specifications in the Applications section.1

CS61584A8 DS261PP5DS261PP5DIGITAL CHARACTERISTICS (TA = -40 to 85 °C; power supply pins within ±5% of nominal.)Notes: 23. Digital inputs are designed

CS61584ADS261PP5 9DS261PP5Any Digital Outputtrtf10% 10%90% 90%Figure 1. Signal Rise And Fall CharacteristicsRCLK(for CLKE = high)RCLK(for CLKE =