Cirrus-logic CS61884 Bedienungsanleitung

1Copyright  Cirrus Logic, Inc. 2011(All Rights Reserved)http://www.cirrus.comCS61884Octal T1/E1/J1 Line Interface Unit Features Industry-standard Fo

CS6188410 DS485F33.2 ControlSYMBOL LQFP LFBGA TYPE DESCRIPTIONMCLK 10 E1 IMaster Clock InputThis pin is a free running reference clock that should be

CS61884DS485F3 11MUX/BITSEN0 43 K2 IMultiplexed Interface/Bits Clock SelectHost Mode -This pin configures the microprocessor inter-face for multiplexe

CS6188412 DS485F3WR/DS/SDI/LEN0 84 J14 IData Strobe/ Write Enable/Serial Data/Line Length InputIntel Parallel Host Mode - This pin “WR” functions as a

CS61884DS485F3 13INTL/MOT/CODEN88 H12 IMotorola/Intel/Coder Mode Select InputParallel Host Mode - When this pin is “Low” the micropro-cessor interface

CS6188414 DS485F33.3 Address Inputs/LoopbacksSYMBOL LQFP LFBGA TYPE DESCRIPTIONA4 12 F4 IAddress Selector InputParallel Host Mode - During non-multip

CS61884DS485F3 153.4 Cable Select3.5 StatusSYMBOL LQFP LFBGA TYPE DESCRIPTIONCBLSEL 93 G13 ICable Impedance SelectHost Mode - The input voltage to t

CS6188416 DS485F33.6 Digital Rx/Tx Data I/OSYMBOL LQFP LFBGA TYPE DESCRIPTIONTCLK0 36 N1 ITransmit Clock Input Port 0- When TCLK is active, the TPOS

CS61884DS485F3 17RCLK0 39 P1 OReceive Clock Output Port 0- When MCLK is active, this pin outputs the recovered clock from the signal input on RTIP and

CS6188418 DS485F3RCLK2 78 M14 O Receive Clock Output Port 2RPOS2/RDATA2 77 M13 O Receive Positive Pulse/ Receive Data Output Port 2RNEG2/BPV2 76 M12 O

CS61884DS485F3 193.7 Analog RX/TX Data I/ORCLK7 143 A1 O Receive Clock Output Port 7RPOS7/RDATA7 142 A2 O Receive Positive Pulse/ Receive Data Output

CS618842 DS485F3TABLE OF CONTENTS1. PINOUT - LQFP ...

CS6188420 DS485F3TTIP2 57 L10 O Transmit Tip Output Port 2TRING2 58 M10 O Transmit Ring Output Port 2RTIP2 60 M8 I Receive Tip Input Port 2RRING2 61 L

CS61884DS485F3 213.8 JTAG Test Interface3.9 MiscellaneousSYMBOL LQFP LFBGA TYPE DESCRIPTIONTRST95 G12 IJTAG ResetThis active Low input resets the JT

CS6188422 DS485F34. OPERATIONThe CS61884 is a full featured line interface unitfor up to eight E1/T1/J1 lines. The device providesan interface to twi

CS61884DS485F3 238. BUILDING INTEGRATED TIMING SYSTEMS (BITS) CLOCK MODEThis mode is used to enable one or more channelsas a stand-alone timing recov

CS6188424 DS485F39. TRANSMITTERThe CS61884 contains eight identical transmittersthat each use a low power matched impedance driv-er to eliminate the

CS61884DS485F3 25The CS61884 also allows the user to customize thetransmit pulse shapes to compensate for non-stan-dard cables, transformers, or prote

CS6188426 DS485F3In host mode, TAOS is generated for a particularchannel by asserting the associated bit in the TAOSEnable Register (03h) (See Section

CS61884DS485F3 27RPOS/RDATA pin. When bipolar violations aredetected by the decoder, the RNEG/BPV pin is as-serted “High”. This pin is driven “high” o

CS6188428 DS485F3During host mode operation, LOS is reported in theLOS Status Monitor Register. Both the LOS pinsand the register bits reflect LOS sta

CS61884DS485F3 2912. OPERATIONAL SUMMARYA brief summary of the CS61884 operations in hardware and host mode is provided in Table 7.12.1 LoopbacksThe

CS61884DS485F3 310.5 Loss-of-Signal (LOS) ...

CS6188430 DS485F312.3 Digital LoopbackDigital Loopback causes the TCLK, TPOS, andTNEG (or TDATA) inputs to be looped backthrough the jitter attenuato

CS61884DS485F3 31EncoderDecoderTNEGTCLKRNEGRCLKTPOSRPOSTTIPTRINGRTIPRRINGClock Recovery &Data RecoveryTransmitControl &Pulse ShaperJitterAtten

CS6188432 DS485F313. HOST MODEHost mode allows the CS61884 to be configuredand monitored using an internal register set. (Referto Table 1, “Operatio

CS61884DS485F3 33As illustrated in Figure 13, the ACB consists of aR/W bit, address field, and two reserved bits. TheR/W bit specifies if the current

CS6188434 DS485F313.4 Register SetThe register set available during host mode opera-tions are presented in Table 9. While the upperthree bits of the

CS61884DS485F3 3514. REGISTER DESCRIPTIONS14.1 Revision/IDcode Register (00h)14.2 Analog Loopback Register (01h)14.3 Remote Loopback Register (02h

CS6188436 DS485F314.7 LOS Interrupt Enable Register (06h)14.8 DFM Interrupt Enable Register (07h)14.9 LOS Interrupt Status Register (08h)14.10 DFM

CS61884DS485F3 3714.13 Digital Loopback Reset Register (0Ch)14.14 LOS/AIS Mode Enable Register (0Dh)14.15 Automatic TAOS Register (0Eh)[3:0] A[3:0]

CS6188438 DS485F314.16 Global Control Register (0Fh)14.17 Line Length Channel ID Register (10h)BIT NAME DescriptionThis register is the global contr

CS61884DS485F3 3914.18 Line Length Data Register (11h)14.19 Output Disable Register (12h)14.20 AIS Status Register (13h)14.21 AIS Interrupt Enable

CS618844 DS485F316.1.2 Test-Logic-Reset ...

CS6188440 DS485F314.22 AIS Interrupt Status Register (15h)14.23 AWG Broadcast Register (16h)14.24 AWG Phase Address Register (17h)14.25 AWG Phase

CS61884DS485F3 4114.27 AWG Overflow Interrupt Enable Register (1Ah)14.28 AWG Overflow Interrupt Status Register (1Bh)14.29 Reserved Register (1Ch)1

CS6188442 DS485F314.33 Status RegistersThe following Status registers are read-only: LOSStatus Register (04h) (See Section 14.5 onpage 35), DFM Statu

CS61884DS485F3 4315. ARBITRARY WAVEFORM GENERATORUsing the Arbitrary Waveform Generator (AWG)allows the user to customize the transmit pulseshapes to

CS6188444 DS485F3channel or channels. To enable the AWG functionfor a specific channel or channels the correspond-ing bit(s) in the AWG Enable Registe

CS61884DS485F3 4516. JTAG SUPPORTThe CS61884 supports the IEEE Boundary ScanSpecification as described in the IEEE 1149.1 stan-dards. A Test Access P

CS6188446 DS485F316.1.4 Select-DR-Scan This is a temporary controller state. 16.1.5 Capture-DR In this state, the Boundary Scan Register capturesinp

CS61884DS485F3 4716.1.11 Select-IR-ScanThis is a temporary controller state. The test dataregister selected by the current instruction retainsits pre

CS6188448 DS485F316.3 Device ID Register (IDR)Revision section: 0h = Rev A, 1h = Rev B and so on. The device Identification Code [27 - 12] is derived

CS61884DS485F3 4928 LOOP1/D1 I LPI129 LOOP1/D1 O LPO130 LOOP2/D2 I LPT231 LOOP2/D2 I LPI232 LOOP2/D2 O LPO233 LOOP3/D3 I LPT334 LOOP3/D3 I LPI335 LOOP

CS61884DS485F3 5LIST OF FIGURESFigure 1. CS61884 144-LQFP Pinout ...

CS6188450 DS485F373 TCLK3 I TCLK374 LOS2 O LOS275 RNEG2 O RNEG276 RPOS2 O RPOS277 RCLK2 O RCLK278 - Note 2 HIZ2_B79 TNEG2 I TNEG280 TPOS2 I TPOS281 TC

CS61884DS485F3 5118. APPLICATIONSFigure 17. Internal RX/TX Impedance Matching+RGND+3.3VRV+T1 1:2REFCS61884One ChannelTRINGTTIPTRANSMITLINET2 1:2RTIP

CS6188452 DS485F3Figure 18. Internal TX, External RX Impedance Matching+RGND0.1μF+3.3VRV+T1 1:2REFTRINGTTIPT2 1:2RTIPRRINGR1R213.3kΩGNDCBLSELTV+VCCIO

CS61884DS485F3 5318.1 Transformer specificationsRecommended transformer specifications areshown in Table 12. Any transformer used with theCS61884 sho

CS6188454 DS485F319. CHARACTERISTICS AND SPECIFICATIONS19.1 Absolute Maximum RatingsCAUTION: Operations at or beyond these limits may result in perm

CS61884DS485F3 5519.3 Digital Characteristics(TA = -40°C to 85°C; TV+, RV+ = 3.3 V ±5%; GND = 0 V)19.4 Transmitter Analog Characteristics (TA = -40°

CS6188456 DS485F319.5 Receiver Analog Characteristics(TA = -40°C to 85°C; TV+, RV+ = 3.3 V ±5%; GND = 0 V)) Notes: 11. Parameters guaranteed by desig

CS61884DS485F3 5719.6 Jitter Attenuator Characteristics(TA = -40°C to 85°C; TV+, RV+ = 3.3 V ±5%; GND = 0 V)Notes: 18. Attenuation measured with sinu

CS6188458 DS485F31101001K 10K0Attenuation in dBFrequency in Hz+ 0.52571.4K20 40040+ 10- 10- 20- 30- 50- 40- 60- 19.5- 6- 70100KAT&T 62411Minimum A

CS61884DS485F3 5919.7 Master Clock Switching Characteristics19.8 Transmit Switching Characteristics19.9 Receive Switching Characteristics* All para

CS618846 DS485F3LIST OF TABLESTable 1. Operation Mode Selection ...

CS6188460 DS485F3RCLKtsuRPOS/RNEGCLKE = 1tsuththRPOS/RNEGCLKE = 0Figure 21. Recovered Clock and Data Switching CharacteristicsTPOS/TNEGTCLKtpw2tpwh2t

CS61884DS485F3 6119.10 Switching Characteristics - Serial PortNotes: 23. If SPOL = 0, then CS should return high no sooner than 20 ns after the 16th

CS6188462 DS485F319.11 Switching Characteristics - Parallel Port (Multiplexed Mode) * All paramters guaranteed by production, characterization or des

CS61884DS485F3 63ALEWRD[7:0]RDYHIGH-ZHIGH-ZCS112 47698352131514ADDRESS Write DataFigure 26. Parallel Port Timing - Write; Intel Multiplexed Address /

CS6188464 DS485F3D[7:0]R/WDSASWrite DataHIGH-Z HIGH-ZADDRESS1524316171876CS8129ACKFigure 28. Parallel Port Timing - Write in Motorola Multiplexed Add

CS61884DS485F3 6519.12 Switching Characteristics- Parallel Port (Non-multiplexed Mode) * All paramters guaranteed by production, characterization or

CS6188466 DS485F3A[4:0]D[7:0]ALERDYWR(pulled high)CSHIGH-Z1710HIGH-Z11 1225346ADDRESSWrite DataFigure 30. Parallel Port Timing - Write in Intel Non-M

CS61884DS485F3 67(pulled high)HIGH-Z1713HIGH-Z1415253 46ADDRESSWrite DataACKD[7:0]CSR/WDSASA[4:0]Figure 32. Parallel Port Timing - Write in Motorola

CS6188468 DS485F319.13 Switching Characteristics - JTAGParameter Symbol Min. Max UnitsCycle Time tcyc200 - nSTMS/TDI to TCK Rising Setup Time tsu50 -

CS61884DS485F3 6920. COMPLIANT RECOMMENDATIONS AND SPECIFICATIONSAT&T Pub 62411FCC Part 68ANSI T1.102 ANSI T1.105ANSI T1.231ANSI T1.403ANSI T1.40

CS61884DS485F3 71. PINOUT - LQFP144143142140139138137136135141134133132131130129128127126125124123122121120CS61884144-PinLQFP373839414243444546404748

CS6188470 DS485F321. LFBGA PACKAGE DIMENSIONS

CS61884DS485F3 7122. LQFP PACKAGE DIMENSIONS INCHES MILLIMETERSDIM MIN NOM MAX MIN NOM MAXA --- 0.55 0.063 --- 1.40 1.60A1 0.002 0.004 0.006 0.05

CS6188472 DS485F323. ORDERING INFORMATION 24. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION* MSL (Moisture Sensitivity Level) as specifie

CS618848 DS485F32. PINOUT - LFBGA1234567891011121314CLKETDOCBLSELREFTPOS5RPOS4TPOS4RPOS5TPOS2RPOS3TPOS3RPOS2TTIP5TRING4TTIP4TRING5TTIP2TRING3TTIP3TRI

CS61884DS485F3 93. PIN DESCRIPTIONS3.1 Power SuppliesSYMBOL LQFP LFBGA TYPE DESCRIPTIONVCCIO1792G1G14Power Supply, Digital Interface: Power supply f