Cirrus-logic CDB4270 Bedienungsanleitung

Copyright © Cirrus Logic, Inc. 2006(All Rights Reserved)http://www.cirrus.comEvaluation Board for CS4270Features Single-Ended Analog Audio Inputs and

10 DS686DB3CDB42702.3 Internal Data RoutingFigure 4 shows the internal data routing topology between the CS4270, CS8416, CS8406 and the DSPHeader. Ref

DS686DB3 11CDB42702.4 Internal DriversFigure 5 shows the internal drivers and logic for board level selects/enables and so forth. Refer to the FPGAGUI

12 DS686DB3CDB42702.5 External MCLK ControlSeveral sources for MCLK exist on the CDB4270. The crystal oscillator, Y1, will master the MCLK bus whenno

DS686DB3 13CDB42703. SOFTWARE MODEThe CDB4270 uses a Microsoft Windows-based GUI (download from Cirrus web site), which allows control of theCS4270 an

14 DS686DB3CDB42703.2 CDB4270 GUIBrief descriptions of the GUI tab views are provided below.The CDB4270 Controls tab provides high-level control of th

DS686DB3 15CDB42703.3 Register Maps Control TabsUnder this tab are the CS4270, Board Configuration (FPGA) and GPIO tabs. On each tab, register valuesc

16 DS686DB3CDB4270Figure 9. Register Maps Tab - Board Configuration

DS686DB3 17CDB4270 Figure 10. Register Maps Tab - GPIO

18 DS686DB3CDB42704. HARDWARE MODEWhen the Flex GUI is not running on a PC or when the USB or serial port cables are not connected to the CDB4270from

DS686DB3 19CDB42705.2 FPGA CODE REVISION ID - ADDRESS 00H5.2.1 Revision Number Bits (Bits 7:0)Function:Identifies FPGA code revision number. REV.7 - R

2 DS686DB3CDB4270TABLE OF CONTENTS1. SYSTEM OVERVIEW ...

20 DS686DB3CDB42705.3 CS4270 CONTROL - ADDRESS 01H5.3.1 SDOUT Routing to Header (Bits 7:6)Default = 00Function:These bits control the routing of SDOUT

DS686DB3 21CDB42705.3.4 Subclock Routing (Bits 1:0)Default = 00Function:These bits select SCLK and LRCK routing to/from the CS4270, CS8416, CS8406 and

22 DS686DB3CDB42705.4.2 CS8406 Master/Slave Select (Bit 4)Default = 0Function:This bit selects CS8406 Master Mode (SCLK, LRCK are outputs) or Slave Mo

DS686DB3 23CDB42705.5 CS8416 RX CONTROL - ADDRESS 03H5.5.1 CS8416 RMCLK Divider Control (Bit 6)Default = 0Function:This bit selects the CS8416 RMCLK d

24 DS686DB3CDB42706. CDB4270 HARDWARE MODE SETTINGSSchematic-Level Functional Description:When the Flex GUI is not used and there is no serial port co

DS686DB3 25CDB42701. For other M1, M0, MDIV2, MDIV1 states, CS8406 OMCLK=256xFs and CS8416 RMCLK=256xFs.Note: Whenever changes are made to the S/PDIF

26 DS686DB3CDB42707. CDB CONNECTORS, SWITCHES, INDICATORS AND JUMPERS CONNECTOR,SWITCHReferenceDesignator INPUT/OUTPUT SIGNAL PRESENT+5V J1 Input +5.

DS686DB3 27CDB42708. ADC PERFORMANCE PLOTS-150+0-140-130-120-110-100-90-80-70-60-50-40-30-20-10dBFS20 20k50 100 200 500 1k 2k 5k 10kHz-150+0-140-130-1

28 DS686DB3CDB4270-5+5-4-3-2-1+0+1+2+3+4dBFS20 20k50 100 200 500 1k 2k 5k 10kHz-150+0-140-130-120-110-100-90-80-70-60-50-40-30-20-10dBFS20 20k50 100 2

DS686DB3 29CDB4270-110+0-100-90-80-70-60-50-40-30-20-10dBFS-120 +0-100 -80 -60 -40 -20dBr-40+40-35-30-25-20-15-10-5+0+5+10+15+20+25+30+35dBFS-140 +0-1

DS686DB3 3CDB4270LIST OF FIGURESFigure 1.ADC THD+N ...

30 DS686DB3CDB4270-150+0-140-130-120-110-100-90-80-70-60-50-40-30-20-10dBFS20 20k50 100 200 500 1k 2k 5k 10kHz-110+0-100-90-80-70-60-50-40-30-20-10dBF

DS686DB3 31CDB42709. DAC PERFORMANCE PLOTS-150+0-140-130-120-110-100-90-80-70-60-50-40-30-20-10dBr A20 20k50 100 200 500 1k 2k 5k 10kHz-150+0-140-130-

32 DS686DB3CDB4270-40+40-35-30-25-20-15-10-5+0+5+10+15+20+25+30+35dBr A-140 +0-120 -100 -80 -60 -40 -20dBFS-5+5-4-3-2-1+0+1+2+3+4dBr A20 20k50 100 200

DS686DB3 33CDB4270-150+0-140-130-120-110-100-90-80-70-60-50-40-30-20-10dBr A20 20k50 100 200 500 1k 2k 5k 10kHz-150+0-140-130-120-110-100-90-80-70-60-

34 DS686DB3CDB4270-150+0-140-130-120-110-100-90-80-70-60-50-40-30-20-10dBr A20 20k50 100 200 500 1k 2k 5k 10kHzTTT T TTT T T T T T T TTTTTTT TTT T TTT

DS686DB3 35CDB4270-110+0-100-90-80-70-60-50-40-30-20-10dBr A20 20k50 100 200 500 1k 2k 5k 10kHz-110+0-100-90-80-70-60-50-40-30-20-10dBr A-120 +0-100 -

36 DS686DB3CDB427010.CDB BLOCK DIAGRAM Figure 65. Block DiagramCS4270CS8416S/PDIF InputSingle-Ended OutputSingle-Ended InputUSB/Serial Control Po

DS686DB3 37CDB427011.CDB SCHEMATICS Figure 66. CS4270

38 DS686DB3CDB4270 Figure 67. Analog Input

DS686DB3 39CDB4270Figure 68. Analog Output

4 DS686DB3CDB4270Figure 53.96 kHz, Crosstalk ...

40 DS686DB3CDB4270 Figure 69. CS8406 S/PDIF Transmitter

DS686DB3 41CDB4270 Figure 70. CS8416 S/PDIF Receiver

42 DS686DB3CDB4270 Figure 71. Buffers - Clock/Data Routing

DS686DB3 43CDB4270 Figure 72. FPGA

44 DS686DB3CDB4270 Figure 73. USB/RS232 Microprocessor

DS686DB3 45CDB4270 Figure 74. Power

46 DS686DB3CDB427012.CDB LAYOUT Figure 75. Silk Screen

DS686DB3 47CDB4270 Figure 76. Top-Side Layer

48 DS686DB3CDB4270 Figure 77. Bottom-Side Layer

DS686DB3 49CDB427013.CHANGES MADE TO REV. B BOARD13.1 Modifications (Done by Cirrus Logic)Note: There is no rework necessary when CS4270 C0 parts are

DS686DB3 5CDB42701. SYSTEM OVERVIEW The CDB4270 evaluation board is an excellent tool for evaluating the CS4270 CODEC. The board features bothanalog a

50 DS686DB3CDB427014.REVISION HISTORYRevision ChangesDB1 Initial Release: Applies to A Assy. (A2 PL).DB2This Revision is for the B Assy. (B2 PL). Upda

6 DS686DB3CDB42701.7 Canned OscillatorOscillator Y1 provides a system master clock. This clock is routed through the CS8416 and out of the RMCKpin whe

DS686DB3 7CDB4270Figure 1. ADC THD+NFigure 2. ADC Dynamic Range

8 DS686DB3CDB42701.10 Analog OutputsThe CS4270 analog outputs are AC-coupled and routed through a single-pole RC Low-Pass filter.1.11 Control PortA gr

DS686DB3 9CDB42702. FPGA OVERVIEWThe FPGA (U11) controls all digital signal routing between the CS4270, CS8406, CS8416 and the DSP I/O Header.The devi