Cirrus-logic CS61880 Bedienungsanleitung PDF herunterladen (Seite 50)

CS61880

50 DS450PP3

18. APPLICATIONS

Figure 16. Internal RX/TX Impedance Matching

RGND

+3.3V

RV+

T1 1:2

REF

CS61880

One Channel

TRING

TTIP

TRANSMIT

LINE

T2 1:1.15

RTIP

RRING

13.3k

Ω

GND

CBLSEL

TV+

VCCIO

+3.3V

TGND

GNDIO

Ω

Cable

120

Ω

Cable

+3.3V

0.1

RECEIVE

LINE

Note 2

Note 1

Notes:1) Required Capacitor between each TV+, RV+, VCCIO and TGND, RGND, GNDIO respec-

tively.

2) Common decoupling capacitor for all TVCC and TGND pins.

Component E1 75Ω Coaxial Cable E1 120Ω Twisted Pair Cable

R1 (Ω) 15 15

R2 (Ω) 15 15

1 2 ... 45 46 47 48 49 50 51 52 53 54 55 ... 69 70

Octal E1 Line Interface Unit 1
TABLE OF CONTENTS 2
LIST OF FIGURES 5
LIST OF TABLES 6
(Top View) 7
160 FBGA 8
(Bottom View) 8
3. PIN DESCRIPTIONS 9
3.1 Power Supplies 9
3.2 Control 10
3.3 Address Inputs/Loopbacks 14
3.4 Cable Select 15
3.6 Digital Rx/Tx Data I/O 16
3.7 Analog RX/TX Data I/O 19
3.8 JTAG Test Interface 21
3.9 Miscellaneous 21
4. OPERATION 22
5. POWER-UP 22
6. MASTER CLOCK 22
7. G.772 MONITORING 22
DS450PP3 23 23
9. TRANSMITTER 24
9.1 Bipolar Mode 24
9.2 Unipolar Mode 24
DS450PP3 25 25
10. RECEIVER 26
10.1 Bipolar Output Mode 26
10.2 Unipolar Output Mode 26
10.3 RZ Output Mode 26
10.5 Loss-of-Signal (LOS) 27
11. JITTER ATTENUATOR 28
12. OPERATIONAL SUMMARY 29
12.1 Loopbacks 29
12.2 Analog Loopback 29
12.3 Digital Loopback 30
12.4 Remote Loopback 30
13. HOST MODE 32
13.1 SOFTWARE RESET 32
13.2 Serial Port Operation 32
13.3 Parallel Port Operation 33
13.4 Register Set 34
TAOS Enable Register (03h) 35
DFM Status Register (05h) 35
DS450PP3 41 41
15. ARBITRARY WAVEFORM 42
GENERATOR 42
16. JTAG SUPPORT 43
18. APPLICATIONS 50
18.3 Line Protection 52
19.3 Digital Characteristics 54
Attenuation in dB 56
Frequency in Hz 56
DS450PP3 57 57
RPOS/RNEG 59
CLKE = 1 59
CLKE = 0 59
62 DS450PP3 62
DS450PP3 63 63
64
DS450PP3 65 65
66 DS450PP3 66
68 DS450PP3 68
DS450PP3 69 69

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