Cirrus-logic CS42526 Bedienungsanleitung PDF herunterladen (Seite 59)

DS585F2 59

CS42526

Mixing Control Pair 2 (Channels A2 & B2) (address 19h)

Mixing Control Pair 3 (Channels A3 & B3) (address 1Ah)

6.15.1 CHANNEL A VOLUME = CHANNEL B VOLUME (PX_A=B)

Default = 0

0 - Disabled

1 - Enabled

Function:

The AOUTAx and AOUTBx volume levels are independently controlled by the A and the B Channel

Volume Control registers when this function is disabled. The volume on both AOUTAx and AOUTBx

are determined by the A Channel Volume Control registers (per A-B pair), and the B Channel Volume

Control registers are ignored when this function is enabled.

76543210

Px_A=B Reserved Reserved Px_ATAPI4 Px_ATAPI3 Px_ATAPI2 Px_ATAPI1 Px_ATAPI0

1 2 ... 54 55 56 57 58 59 60 61 62 63 64 ... 90 91

Features 1
General Description 1
TABLE OF CONTENTS 2
LIST OF FIGURES 4
LIST OF TABLES 5
ABSOLUTE MAXIMUM RATINGS 6
ANALOG INPUT CHARACTERISTICS 7
ANALOG OUTPUT CHARACTERISTICS 9
SWITCHING CHARACTERISTICS 11
FORMAT 13
DC ELECTRICAL CHARACTERISTICS 14
A (Note 28)Serial Port 15
2. PIN DESCRIPTIONS 16
DS585F2 17 17
18 DS585F2 18
DS585F2 19 19
4. APPLICATIONS 20
4.3 Analog Outputs 21
4.3.2 Interpolation Filter 21
4.3.4 ATAPI Specification 22
4.5 Clock Generation 24
Clock Generation 24
4.5.2 OMCK System Clock Mode 25
4.5.3 Master Mode 25
4.5.4 Slave Mode 25
4.6 Digital Interfaces 26
DS585F2 29 29
Left Channel Right Channel 30
CX_SDOUT 30
SAI_SDOUT 30
MSB LSB MSB LSB 31
4.6.4.1 OLM Config #1 32
4.6.4.2 OLM Config #2 33
4.6.4.3 OLM Config #3 34
4.6.4.4 OLM Config #4 35
4.6.4.5 OLM Config #5 36
4.7.1 SPI Mode 37
4.7.2 I²C Mode 38
4.8 Interrupts 39
4.9 Reset and Power-Up 39
5. REGISTER QUICK REFERENCE 41
42 DS585F2 42
Addr Function 7 6 5 4 3 2 1 0 42
DS585F2 43 43
44 DS585F2 44
6. REGISTER DESCRIPTION 45
76543210 46
Table 5. DAC De-Emphasis 48
Table 6. Receiver De-Emphasis 48
Table 8. ADC One-Line Mode 49
Table 9. DAC One-Line Mode 49
Table 16. ATAPI Decode 60
7. PARAMETER DEFINITIONS 72
8.1 ADC Input Filter 73
8.2 DAC Output Filter 73
9.2.1.1 One-Byte Mode 75
9.2.1.2 Two-Byte Mode 75
9.3.1.1 Format Detection 76
10.APPENDIX C: PLL FILTER 77
10.1.2 Jitter Attenuation 79
10.1.3 Capacitor Selection 80
10.1.4 Circuit Board Layout 81
COMPONENTS 82
DS585F2 83 83
84 DS585F2 84
84
DS585F2 85 85
86 DS585F2 86
DS585F2 87 87
88 DS585F2 88
14.PACKAGE DIMENSIONS 89
THERMAL CHARACTERISTICS 89
64L LQFP PACKAGE DRAWING 89
15.ORDERING INFORMATION 90
16.REFERENCES 90
17.REVISION HISTORY 91

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