Cirrus-logic CS5378 Bedienungsanleitung

Copyright  Cirrus Logic, Inc. 2010(All Rights Reserved)http://www.cirrus.comCS5378Low-power Single-channel Decimation FilterFeatures Single-channel

CS5378DS639F3 10Bits 23:20 19:16 15:12 11:8 7:4 3:0Selection 0000 0000 IIR2 IIR1 FIR2 FIR1Figure 3. FIR and IIR Coefficient Set Selection WordBits 15

CS5378DS639F3 11SPI RegistersDigital Filter RegistersName Addr. Type # Bits DescriptionSPICTRL 00 - 02 R/W 8, 8, 8 SPI ControlSPICMD 03 - 05 R/W 8, 8,

CS5378DS639F3 122. CHARACTERISTICS AND SPECIFICATIONS• Min / Max characteristics and specifications are guaranteed over the Specified Operating Condit

CS5378DS639F3 13THERMAL CHARACTERISTICS DIGITAL CHARACTERISTICS Notes: 2. Maximum leakage for pins with pull-up resistors (RESET, SS:EECS, GPIO, MOSI,

CS5378DS639F3 14SWITCHING CHARACTERISTICS Serial Configuration Interface Timing (External Master)Parameter Symbol Min Typ Max UnitMOSI Write TimingSS

CS5378DS639F3 15SWITCHING CHARACTERISTICS Serial Data Interface TimingParameter Symbol Min Typ Max UnitDRDY Falling Edge to SCK Rising t160 - - nsSCK

CS5378DS639F3 16SWITCHING CHARACTERISTICS CLK, SYNC, MCLK, MSYNC, and MDATANotes: 3. PLL bypass mode. The PLL generates a 32.768 MHz master clock whe

CS5378DS639F3 17SWITCHING CHARACTERISTICS Test Bit Stream (TBS)5. TBSDATA can be delayed from 0 to 63 full bit periods. The timing diagram shows no TB

CS5378DS639F3 183. SYSTEM DESIGN WITH CS5378Figure 9 illustrates a simplified block diagram ofthe CS5378 in a single channel measurement sys-tem.A dif

CS5378DS639F3 193.4 SynchronizationDigital filter phase and analog sample timing of theΔΣ modulator connected to the CS5378 are syn-chronized by a ris

CS5378DS639F3 2TABLE OF CONTENTS1. General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61.1. Digital Fi

CS5378DS639F3 204. POWER SUPPLIESThe CS5378 has three sets of power supply inputs.One set supplies power to the I/O pins of the device(VDDPAD), anothe

CS5378DS639F3 215. RESET CONTROLThe CS5378 reset signal is active low. When re-leased, a series of self-tests are performed and thedevice either acti

CS5378DS639F3 226. PLL AND CLOCK GENERATIONThe CS5378 requires a 32.768 MHz master clock,which can be supplied directly or from an internalphase locke

CS5378DS639F3 236.4 Master Clock Jitter and SkewCare must be taken to minimize jitter and skew onthe distributed system clock as both parameters af-fe

CS5378DS639F3 247. SYNCHRONIZATIONThe CS5378 has a dedicated SYNC input thataligns the internal digital filter phase and generatesan external signal f

CS5378DS639F3 258. CONFIGURATION BY EEPROM After reset, the CS5378 reads the state of theGPIO7:BOOT pin to determine a source for con-figuration comma

CS5378DS639F3 26SCKMOSISS:EECSMSB LSBMISOX612345MSB LSB61234518276543CycleMOSIMISO0x03 ADDRDATA1 DATA3DATA2SS:EECSREAD1 BYTE / 3 BYTEADDRCMDADDRDATA2

CS5378DS639F3 27The maximum number of bytes that will be writtenfor a single configuration is less than 2 KByte(16 Kbit), including command overhead:S

CS5378DS639F3 28Sample Command:Write IIR1 coefficients 0x84BC9D, 0x7DA1B1,0x825E4F, and IIR2 coefficients 0x83694F,0x3CAD5F, 0x3E5104, 0x835DF8, 0x3E5

CS5378DS639F3 298.5 Example EEPROM ConfigurationTable 8 shows an example EEPROM file for a min-imal CS5378 configuration.Table 8. Example EEPROM FileA

CS5378DS639F3 39.1. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309.2. Microcontroller Har

CS5378DS639F3 309. CONFIGURATION BY MICROCONTROLLERAfter reset, the CS5378 reads the state of theGPIO7:BOOT pin to determine a source for con-figurati

CS5378DS639F3 31SCKMOSIFigure 18. Microcontroller Serial TransactionsSS:EECSMSB LSBMISOX612345MSB LSB61234518276543CycleMISO 0x02 ADDR Data1MOSIMISOM

CS5378DS639F3 329.3.2 SPI registersThe SPI registers are shown in Figure 19 and are24-bit registers mapped into an 8-bit register spaceas high, mid, a

CS5378DS639F3 339.4 Microcontroller Configuration CommandsA summary of available microcontroller configura-tion commands is listed in Table 9.Write DF

CS5378DS639F3 34Write FIR Coefficients - 0x03This command writes custom coefficients for theFIR1 and FIR2 filters. The first two data words setthe num

CS5378DS639F3 359.5 Example Microcontroller ConfigurationTable 10 shows an example microcontroller trans-actions for a minimal CS5378 configuration.Ta

CS5378DS639F3 3610.MODULATOR INTERFACEThe CS5378 performs digital filtering for a ΔΣ typemodulator. Signals from the ΔΣ modulators areconnected throu

CS5378DS639F3 3710.4 Modulator Data InputThe MDATA input expects 1-bit ΔΣ data at a512 kHz or 256 kHz rate. The input rate is selectedby a bit in the

CS5378DS639F3 3811.DIGITAL FILTER INITIALIZATIONThe CS5378 digital filter consists of three multi-stage sections: a three stage SINC filter, a two sta

CS5378DS639F3 3911.2.2 Output Word RateThe CS5378 digital filter supports output word rates (OWRs) between 4000 SPS and 1 SPS. The outputword rate is

CS5378DS639F3 417.7. TBS Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6218. Time Break Controller. . .

CS5378DS639F3 4012.SINC FILTERThe SINC filter primary purpose is to attenuate out-of-band noise components from the ΔΣ modula-tors. While doing so, t

CS5378DS639F3 41Figure 24. SINC Filter StagesSINC1 – Single stage, fixed decimate by 8 5th order decimate by 8, 36 coefficients SINC2 – Multi-stag

CS5378DS639F3 42Filter Type System Function Filter Coefficients SINC2 (Stage 1) SINC2 (Stage 2) 4th order decimate by 2 5 coefficients 41211)(

CS5378DS639F3 43Table 13. SINC3 Filter CoefficientsFilter Type System Function Filter Coefficients SINC3 (Stage 1) SINC3 (Stage 2) SINC3 (Stage 3) 4

CS5378DS639F3 4413.FIR FILTERThe finite impulse response (FIR) filter block consists of two cascaded stages, FIR1 and FIR2. It compen-sates for SINC

CS5378DS639F3 4513.3 On-Chip FIR CoefficientsTwo sets of on-chip coefficients, linear phase andminimum phase, are available for FIR1 and FIR2.Performa

CS5378DS639F3 46FIR1 – Single stage, fixed decimate by 4 Coefficient set 0: linear phase decimate by 4, 48 coefficients Coefficient set 1: minimum ph

CS5378DS639F3 47Table 15. SINC + FIR Group DelayIndividual filter stage group delay (no IIR) Decimation Ratios Number of Coefficients Group Delay (In

CS5378DS639F3 48Minimum phase group delay FIR1 Minimum Phase Group Delay (Normalized frequency) FIR2 Minimum Phase Group Delay (Normalized frequen

CS5378DS639F3 49Filter Type Filter Coefficients (normalized 24-bit) FIR1 (Coefficient set 0) Low pass, SINC compensation Linear phase decimate by 4 4

CS5378DS639F3 5Figure 29. FIR2 Minimum Phase Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Figure 30. IIR Filter B

CS5378DS639F3 50Filter Type Filter Coefficients (normalized 24-bit) FIR2 (Coefficient set 0) Low pass, passband to 40% fs Linear phase decimate by 2

CS5378DS639F3 51Filter Type Filter Coefficients (normalized 24-bit) FIR2 (Coefficient set 1) Low pass, passband to 40% fs Minimum phase decimate by 2

CS5378DS639F3 5214.IIR FILTERThe infinite impulse response (IIR) filter blockconsists of two cascaded stages, IIR1 and IIR2. Itcreates a high-pass co

CS5378DS639F3 53characteristic equations model the operation of the2nd order IIR filter with unnormalized coefficients.W5 = W4W4 = W3W3 = X + (-a21 *

CS5378DS639F3 54IIR1 – Single stage, no decimation 1st order no decimation, 3 coefficients Coefficient set 0: high-pass, corner 0.15% fs (3 Hz at 20

CS5378DS639F3 55Filter Type System Function Filter Coefficients (normalized 24-bit) IIR1 (Coefficient set 0) 1st order, high pass Corner at 0.15% fs

CS5378DS639F3 5615.GAIN AND OFFSET CORRECTIONThe CS5378 digital filter can apply gain and offsetcorrections to the measurement data. Also, an off-set

CS5378DS639F3 57and a maximum negative value of 0x800000. If ap-plying an offset correction causes the final result toexceed a 24-bit two’s complemen

CS5378DS639F3 5816.SERIAL DATA INTERFACEOnce digital filtering is complete, each 24-bit out-put sample is combined with an 8-bit status byte.These dat

CS5378DS639F3 59ceived, the MFLAG bit is set in the next outputword. See “Modulator Interface” on page 36 formore information about MFLAG.Time Break B

CS5378DS639F3 61. GENERAL DESCRIPTIONThe CS5378 is a single channel digital filter withintegrated system peripherals. Figure 1 illustrates asimplified

CS5378DS639F3 6017.TEST BIT STREAM GENERATORThe CS5378 test bit stream (TBS) generator createssine wave ΔΣ bit stream data to drive an externaltest DA

CS5378DS639F3 61Data Delay - DDLY[5:0]Programs full period delays for TBSDATA, up to amaximum of 63 bits.Gain - TBSGAIN[23:0]Scales the amplitude of t

CS5378DS639F3 6217.6 TBS Loopback TestingIncluded as part of the CS5378 test bit stream gen-erator is a feedback path to the digital filter MDA-TA inp

CS5378DS639F3 6318.TIME BREAK CONTROLLERA time break signal is used to mark timing eventsthat occur during measurement. An external signalsets a flag

CS5378DS639F3 6419.GENERAL PURPOSE I/OThe General Purpose I/O (GPIO) block provides 8general purpose pins to interface with externalhardware.19.1 Pin

CS5378DS639F3 6519.5.1 GPIO Reads in Output ModeWhen reading GPIO pins the GP_DATA registervalue always reports the current state of the pins, soa val

CS5378DS639F3 6620.REGISTER SUMMARY20.1 SPI RegistersThe CS5378 SPI registers interface the serial port to the digital filter.Name Addr. Type # Bits D

CS5378DS639F3 6720.1.1 SPICTRL : 0x00, 0x01, 0x02 (MSB) 23 22 21 20 19 18 17 16-- -- -- -- -- -- -- --R/W R/W1 R/W R/W R/W R/W R/W R/W0000101115

CS5378DS639F3 6820.1.2 SPICMD : 0x03, 0x04, 0x05 (MSB) 23 22 21 20 19 18 17 16SCMD23 SCMD22 SCMD21 SCMD20 SCMD19 SCMD18 SCMD17 SCMD16R/WR/WR/WR/W

CS5378DS639F3 6920.1.3 SPIDAT1 : 0x06, 0x07, 0x08 (MSB) 23 22 21 20 19 18 17 16SDAT23 SDAT22 SDAT21 SDAT20 SDAT19 SDAT18 SDAT17 SDAT16R/WR/WR/WR/

CS5378DS639F3 7DC offset.- Calibration engine for automatic calcula-tion of offset correction factor.1.2 Integrated Peripheral Features• Low jitter PL

CS5378DS639F3 7020.1.4 SPIDAT2 : 0x09, 0x0A, 0x0B (MSB) 23 22 21 20 19 18 17 16SDAT23 SDAT22 SDAT21 SDAT20 SDAT19 SDAT18 SDAT17 SDAT16R/WR/WR/WR/

CS5378DS639F3 7120.2 Digital Filter RegistersThe CS5378 digital filter registers control hardware peripherals and filtering functions.Name Addr. Type

CS5378DS639F3 7220.2.1 CONFIG : 0x00(MSB)2322212019181716-- -- -- -- -- DFS2 DFS1 DFS0R/W R/W R/W R/W R/W R/W R/W R/W0000010115 14 13 12 11 10 9 8-- -

CS5378DS639F3 7320.2.2 GPCFG : 0x0E (MSB) 23 22 21 20 19 18 17 16GP_DIR7 GP_DIR6 GP_DIR5 GP_DIR4 GP_DIR3 GP_DIR2 GP_DIR1 GP_DIR0R/WR/WR/WR/WR/WR/

CS5378DS639F3 7420.2.3 FILTCFG : 0x20 (MSB) 23 22 21 20 19 18 17 16-- -- -- EXP4 EXP3 EXP2 EXP1 EXP0R/WR/WR/WR/WR/WR/WR/WR/W0000000015 14 13 12 1

CS5378DS639F3 7520.2.4 GAIN : 0x21 (MSB) 23 22 21 20 19 18 17 16GAIN23 GAIN22 GAIN21 GAIN20 GAIN19 GAIN18 GAIN17 GAIN16R/WR/WR/WR/WR/WR/WR/WR/W00

CS5378DS639F3 7620.2.5 OFFSET : 0x25 (MSB) 23 22 21 20 19 18 17 16OFST23 OFST22 OFST21 OFST20 OFST19 OFST18 OFST17 OFST16R/WR/WR/WR/WR/WR/WR/WR/W

CS5378DS639F3 7720.2.6 TIMEBRK : 0x29 (MSB) 23 22 21 20 19 18 17 16TBRK23 TBRK22 TBRK21 TBRK20 TBRK19 TBRK18 TBRK17 TBRK16R/WR/WR/WR/WR/WR/WR/WR/

CS5378DS639F3 7820.2.7 TBSCFG : 0x2A (MSB) 23 22 21 20 19 18 17 16INTP7 INTP6 INTP5 INTP4 INTP3 INTP2 INTP1 INTP0R/WR/WR/WR/WR/WR/WR/WR/W00000000

CS5378DS639F3 7920.2.8 TBSGAIN : 0x2B (MSB) 23 22 21 20 19 18 17 16TGAIN23 TGAIN22 TGAIN21 TGAIN20 TGAIN19 TGAIN18 TGAIN17 TGAIN16R/WR/WR/WR/WR/W

CS5378DS639F3 8from 3.3 V or 5 V.- Digital logic core operates from 2.5 V,3.3 V or 5 V.• Small 28-pin SSOP package.- Total footprint 8 mm x 10 mm plus

CS5378DS639F3 8020.2.9 SYSTEM1, SYSTEM2 : 0x2C, 0x2D (MSB) 23 22 21 20 19 18 17 16SYS23 SYS22 SYS21 SYS20 SYS19 SYS18 SYS17 SYS16R/WR/WR/WR/WR/WR

CS5378DS639F3 8120.2.10 VERSION : 0x2E (MSB) 23 22 21 20 19 18 17 16TYPE7 TYPE6 TYPE5 TYPE4 TYPE3 TYPE2 TYPE1 TYPE0R/WR/WR/WR/WR/WR/WR/WR/W011110

CS5378DS639F3 8220.2.11 SELFTEST : 0x2F (MSB) 23 22 21 20 19 18 17 16-- -- -- -- EU3 EU2 EU1 EU0R/WR/WR/WR/WR/WR/WR/WR/W0000101015 14 13 12 11 10

CS5378DS639F3 8321.PIN DESCRIPTION1234567821222324252627289101112 171819201314 1516GPIO0GPIO1GPIO2GPIO3GPIO4:PLL0GPIO5:PLL1GPIO6:PLL2TBSDATAVDDPADGNDP

CS5378DS639F3 84Pin NamePin NumberPin TypePin DescriptionTest Bit StreamTBSDATA 8 Output Test bit stream data output.Modulator InterfaceMCLK 11 Output

CS5378DS639F3 8522.PACKAGE DIMENSIONS INCHES MILLIMETERS NOTEDIM MIN NOM MAX MIN NOM MAXA-- --0.084-- --2.13A1 0.002 0.006 0.010 0.05 0.15 0.25A2 0.06

CS5378DS639F3 8623.ORDERING INFORMATION 24.ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION* MSL (Moisture Sensitivity Level) as specified by

CS5378DS639F3 8725.REVISION HISTORY Revision Date ChangesPP1 FEB 2004 Initial “Preliminary Product” release.F1 OCT 2005 Added lead-free device orderin

CS5378DS639F3 88Contacting Cirrus Logic SupportFor all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one ne

CS5378DS639F3 9Microcontroller Boot Configuration CommandsEEPROM Boot Configuration Commands[DATA] indicates data word returned from digital filter.(D