Copyright Cirrus Logic, Inc. 2011(All Rights Reserved)http://www.cirrus.comCS5461ASingle Phase, Bi-directional Power/Energy ICFeatures• Energy Data
CS5461A10 DS661F3SWITCHING CHARACTERISTICS• Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.• T
CS5461ADS661F3 11t1t2t3t4t5MSBMSB-1LSBMSBMSB-1LSBMSBMSB-1LSBMSBMSB-1LSBCommand Time 8 SCLKs High Byte Mid Byte Low ByteCSSCLKSDIt10t9RESETSDOSCLKCSLas
CS5461A12 DS661F3ABSOLUTE MAXIMUM RATINGSWARNING: Operation at or beyond these limits may result in permanent damage to the device.Normal operation is
CS5461ADS661F3 134. THEORY OF OPERATIONThe CS5461A is a dual-channel analog-to-digital con-verter (ADC) followed by a computation engine that per-form
CS5461A14 DS661F3To generate a value for the accumulated active energyover the last computation cycle, the active power can bemultiplied by the time d
CS5461ADS661F3 155. FUNCTIONAL DESCRIPTION5.1 Analog InputsThe CS5461A is equipped with two fully differential in-put channels. The inputs VIN and I
CS5461A16 DS661F3INT pin will become active if the DRDY bit is unmaskedin the Mask Register. When these bits are set, theymust be cleared (logic 0) by
CS5461ADS661F3 17is (MCLK/K)/16. The pulse duration (tdur) is an integermultiple of MCLK cycles, approximately equal to:The maximum pulse duration (td
CS5461A18 DS661F3energy level, the energy output pins (E1 and E2) alter-nate changing states (see Figure 6). The duration(tedge) between the alternati
CS5461ADS661F3 19EXAMPLE #2:The required number of pulses per unit energy presenton E1 is specified to be 500 pulses per kWhr, given thatthe line volt
CS5461A2 DS661F3TABLE OF CONTENTS1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CS5461A20 DS661F3The Cycle Count Register (N) must be set to a valuegreater than one. Status bit TUP in the Status Register,indicates when the Tempera
CS5461ADS661F3 21dal inputs so there are no problems with slow edgetimes.The CS5461A can be driven by an external oscillatorranging from 2.5 to 20 MHz
CS5461A22 DS661F35.13 Serial Port OverviewThe CS5461A incorporates a serial port transmit and re-ceive buffer with a command decoder that interpretso
CS5461ADS661F3 235.14 CommandsAll commands are 8-bits in length. Any byte that is not listed in this section is invalid. Commands that write to regi
CS5461A24 DS661F35.14.5 Register Read/Write The Read/Write informs the command decoder that a register access is required. During a read operation,
CS5461ADS661F3 255.14.6 Calibration The CS5461A can perform system calibrations. Proper input signals must be applied to the current and voltage c
CS5461A26 DS661F36. REGISTER DESCRIPTION1. “Default” => bit status after power-on or reset2. Any bit not labeled is Reserved. A zero should alway
CS5461ADS661F3 27iCPU Inverts the CPUCLK clock. In order to reduce the level of noise present when analog signals are sampled, the logic driven by CPU
CS5461A28 DS661F36.5 PulseRateE1,2 Register Address: 6 Default = 0xFA000 = 32000.00 HzPulseRateE1,2 sets the frequency of the E1 and/or E2 pulses. Th
CS5461ADS661F3 296.10 Status Register and Mask Register ( Status , Mask )Address: 15 (Status); 26 (Mask)Default = 0x000001 (Status Register), 0x0000
CS5461ADS661F3 36.3 Current and Voltage Gain Register ( Ign ,Vgn ) . . . . . . . . . . . . . . . . . . . . . . . . . . . .276.4 Cycle Count Register
CS5461A30 DS661F36.11 Current and Voltage AC Offset Register ( VACoff , IACoff ) Address: 16 (Current AC Offset); 17 (Voltage AC Offset) Default =
CS5461ADS661F3 316.15 Pulsewidth Register ( PW )Address: 21 Default = 0x000200 = 512 sample periodsPW sets the pulsewidth of E1 and E2 pulses in Alte
CS5461A32 DS661F36.19 No Load Threshold Interval Register ( LoadIntv)Address: 25 Default = 0x000000 = No load threshold feature disabledLoadMin deter
CS5461ADS661F3 336.21 Control Register Register Address: 28 Default = 0x000000FAC Determines if anti-creep is enabled for pulse output E3.0 =
CS5461A34 DS661F36.23 Temperature Offset Register ( Toff )Address: 30 Default = 0xF3D35A = -0.0951126Temperature offset (Toff) is used to remove the
CS5461ADS661F3 357. SYSTEM CALIBRATION7.1 Channel Offset and Gain CalibrationThe CS5461A provides digital DC offset and gain com-pensation that can b
CS5461A36 DS661F3component present in the system during conversioncommands.7.1.2.2 AC Offset Calibration SequenceCorresponding offset registers IACof
CS5461ADS661F3 37ecuted. However, an AC signal should not be used forDC gain calibration.7.1.3.2 DC Gain Calibration SequenceInitiate a DC gain calib
CS5461A38 DS661F38. AUTO-BOOT MODE USING E2PROMWhen the CS5461A MODE pin is asserted (logic 1), theCS5461A auto-boot mode is enabled. In auto-bootmod
CS5461ADS661F3 399. BASIC APPLICATION CIRCUITSFigure 15 shows the CS5461A configured to measurepower in a single-phase, 2-wire system while operatingi
CS5461A4 DS661F3LIST OF FIGURESFigure 1. CS5461A Read and Write Timing Diagrams ...
CS5461A40 DS661F3VA+ VD+CS5461A0.1 µF470 µF500470 nF500NR3R4RBurden1014VIN+9VIN-IIN-101615IIN+PFMONCPUCLKXOUTXINOptionalClockSourceRESET172124CSSDS
CS5461ADS661F3 41VA+ VD+0.1 µF470 µF1k235nF500R1R21014VIN+9VIN-IIN-101615IIN+PFMONCPUCLKXOUTXINOptionalClockSourceRESET172124CSSDISDOSCLKINT0.1 µFV
CS5461A42 DS661F310.PACKAGE DIMENSIONSNotes: 3. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold
CS5461ADS661F3 4311. ORDERING INFORMATION 12. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION* MSL (Moisture Sensitivity Level) as specifie
CS5461A44 DS661F313. REVISION HISTORY Revision Date ChangesA1 DEC 2004 Advance ReleasePP1 FEB 2005 Initial Preliminary ReleaseF1 AUG 2005 Final versio
CS5461ADS661F3 51. OVERVIEWThe CS5461A is a CMOS monolithic power measurement device with a computation engine and an en-ergy-to-frequency pulse outpu
CS5461A6 DS661F32. PIN DESCRIPTIONClock GeneratorCrystal OutCrystal In1,24XOUT, XIN - The output and input of an inverting amplifier. Oscillation occ
CS5461ADS661F3 73. CHARACTERISTICS & SPECIFICATIONSRECOMMENDED OPERATING CONDITIONSANALOG CHARACTERISTICS• Min / Max characteristics and specifica
CS5461A8 DS661F3ANALOG CHARACTERISTICS (Continued)1. Applies when the HPF option is enabled.2. Applies before system calibration.3. All outputs unload
CS5461ADS661F3 9DIGITAL CHARACTERISTICS• Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.• Typic
Kommentare zu diesen Handbüchern