Cirrus-logic CS5461A Bedienungsanleitung

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Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
http://www.cirrus.com
CS5461A
Single Phase, Bi-directional Power/Energy IC
Features
Energy Data Linearity: ±0.1% of Reading over
1000:1 Dynamic Range
On-chip Functions:
- Instantaneous Voltage, Current, and Power
- I
RMS
and V
RMS
, Apparent and Active (Real) Power
- Energy-to-pulse Conversion for Mechanical
Counter/Stepper Motor Drive
- System Calibrations and Phase Compensation
- Temperature Sensor
- Voltage Sag Detect
Meets Accuracy Spec for IEC, ANSI, & JIS.
Low Power Consumption
Current Input Optimized for Sense Resistor.
GND-referenced Signals with Single Supply
On-chip 2.5 V Reference (25 ppm/°C typ)
Power Supply Monitor
Simple Three-wire Digital Serial Interface
“Auto-boot” Mode from Serial E
2
PROM.
Power Supply Configurations:
VA+ = +5 V; AGND = 0 V; VD+ = +3.3 V to +5 V
Description
The CS5461A is an integrated power measure-
ment device which combines two 
analog-to-digital converters, power calculation
engine, energy-to-frequency converter, and a
serial interface on a single chip. It is designed to
accurately measure instantaneous current and
voltage, and calculate V
RMS
, I
RMS
, instanta-
neous power, apparent power, and active power
for single-phase, 2- or 3-wire power metering
applications.
The CS5461A is optimized to interface to shunt
resistors or current transformers for current mea-
surement, and to resistive dividers or potential
transformers for voltage measurement.
The CS5461A features a bi-directional serial in-
terface for communication with a processor, and
a programmable energy-to-pulse output func-
tion. Additional features include on-chip
functionality to facilitate system-level calibration,
temperature sensor, voltage sag detection, and
phase compensation.
ORDERING INFORMATION:
See Page 43.
VA+ VD+
IIN+
IIN-
VIN+
VIN-
VREFIN
VREFOUT
AGND
XIN XOUT CPUCLK DGND
CS
SDO
SDI
SCLK
INT
Voltage
Reference
System
Clock
/K
Clock
Generator
Serial
Interface
E-to-F
Power
Monitor
PFMON
x1
RESET
Digital
Filter
Calibration
MODE
Power
Calculation
Engine
4th Order 
Modulator
2nd Order 
Modulator
Temperature
Sensor
Digital
Filter
PGA
HPF
Option
HPF
Option
E1
E2
E3
x10
APR ‘11
DS661F3
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Inhaltsverzeichnis

Seite 1 - Description

Copyright  Cirrus Logic, Inc. 2011(All Rights Reserved)http://www.cirrus.comCS5461ASingle Phase, Bi-directional Power/Energy ICFeatures• Energy Data

Seite 2 - TABLE OF CONTENTS

CS5461A10 DS661F3SWITCHING CHARACTERISTICS• Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.• T

Seite 3 - DS661F3 3

CS5461ADS661F3 11t1t2t3t4t5MSBMSB-1LSBMSBMSB-1LSBMSBMSB-1LSBMSBMSB-1LSBCommand Time 8 SCLKs High Byte Mid Byte Low ByteCSSCLKSDIt10t9RESETSDOSCLKCSLas

Seite 4 - LIST OF TABLES

CS5461A12 DS661F3ABSOLUTE MAXIMUM RATINGSWARNING: Operation at or beyond these limits may result in permanent damage to the device.Normal operation is

Seite 5 - 1. OVERVIEW

CS5461ADS661F3 134. THEORY OF OPERATIONThe CS5461A is a dual-channel analog-to-digital con-verter (ADC) followed by a computation engine that per-form

Seite 6 - 2. PIN DESCRIPTION

CS5461A14 DS661F3To generate a value for the accumulated active energyover the last computation cycle, the active power can bemultiplied by the time d

Seite 7 - ANALOG CHARACTERISTICS

CS5461ADS661F3 155. FUNCTIONAL DESCRIPTION5.1 Analog InputsThe CS5461A is equipped with two fully differential in-put channels. The inputs VIN and I

Seite 8 - VOLTAGE REFERENCE

CS5461A16 DS661F3INT pin will become active if the DRDY bit is unmaskedin the Mask Register. When these bits are set, theymust be cleared (logic 0) by

Seite 9 - DIGITAL CHARACTERISTICS

CS5461ADS661F3 17is (MCLK/K)/16. The pulse duration (tdur) is an integermultiple of MCLK cycles, approximately equal to:The maximum pulse duration (td

Seite 10 - SWITCHING CHARACTERISTICS

CS5461A18 DS661F3energy level, the energy output pins (E1 and E2) alter-nate changing states (see Figure 6). The duration(tedge) between the alternati

Seite 11 - DS661F3 11

CS5461ADS661F3 19EXAMPLE #2:The required number of pulses per unit energy presenton E1 is specified to be 500 pulses per kWhr, given thatthe line volt

Seite 12 - ABSOLUTE MAXIMUM RATINGS

CS5461A2 DS661F3TABLE OF CONTENTS1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Seite 13 - 4. THEORY OF OPERATION

CS5461A20 DS661F3The Cycle Count Register (N) must be set to a valuegreater than one. Status bit TUP in the Status Register,indicates when the Tempera

Seite 14 - 4.4 Linearity Performance

CS5461ADS661F3 21dal inputs so there are no problems with slow edgetimes.The CS5461A can be driven by an external oscillatorranging from 2.5 to 20 MHz

Seite 15 - 5. FUNCTIONAL DESCRIPTION

CS5461A22 DS661F35.13 Serial Port OverviewThe CS5461A incorporates a serial port transmit and re-ceive buffer with a command decoder that interpretso

Seite 16 - 5.4 Energy Pulse Output

CS5461ADS661F3 235.14 CommandsAll commands are 8-bits in length. Any byte that is not listed in this section is invalid. Commands that write to regi

Seite 17 - Negative Energy

CS5461A24 DS661F35.14.5 Register Read/Write The Read/Write informs the command decoder that a register access is required. During a read operation,

Seite 18 - Pulse Output E3

CS5461ADS661F3 255.14.6 Calibration The CS5461A can perform system calibrations. Proper input signals must be applied to the current and voltage c

Seite 19 - 5.6 No Load Threshold

CS5461A26 DS661F36. REGISTER DESCRIPTION1. “Default” => bit status after power-on or reset2. Any bit not labeled is Reserved. A zero should alway

Seite 20 - 5.10 Power-down States

CS5461ADS661F3 27iCPU Inverts the CPUCLK clock. In order to reduce the level of noise present when analog signals are sampled, the logic driven by CPU

Seite 21 - 5.12 Event Handler

CS5461A28 DS661F36.5 PulseRateE1,2 Register Address: 6 Default = 0xFA000 = 32000.00 HzPulseRateE1,2 sets the frequency of the E1 and/or E2 pulses. Th

Seite 22 - 5.13.1 Serial Port Interface

CS5461ADS661F3 296.10 Status Register and Mask Register ( Status , Mask )Address: 15 (Status); 26 (Mask)Default = 0x000001 (Status Register), 0x0000

Seite 23 - 5.14 Commands

CS5461ADS661F3 36.3 Current and Voltage Gain Register ( Ign ,Vgn ) . . . . . . . . . . . . . . . . . . . . . . . . . . . .276.4 Cycle Count Register

Seite 24 - Active Active (Real) Power

CS5461A30 DS661F36.11 Current and Voltage AC Offset Register ( VACoff , IACoff ) Address: 16 (Current AC Offset); 17 (Voltage AC Offset) Default =

Seite 25 - 5.14.6 Calibration

CS5461ADS661F3 316.15 Pulsewidth Register ( PW )Address: 21 Default = 0x000200 = 512 sample periodsPW sets the pulsewidth of E1 and E2 pulses in Alte

Seite 26 - 6. REGISTER DESCRIPTION

CS5461A32 DS661F36.19 No Load Threshold Interval Register ( LoadIntv)Address: 25 Default = 0x000000 = No load threshold feature disabledLoadMin deter

Seite 27

CS5461ADS661F3 336.21 Control Register Register Address: 28 Default = 0x000000FAC Determines if anti-creep is enabled for pulse output E3.0 =

Seite 28

CS5461A34 DS661F36.23 Temperature Offset Register ( Toff )Address: 30 Default = 0xF3D35A = -0.0951126Temperature offset (Toff) is used to remove the

Seite 29

CS5461ADS661F3 357. SYSTEM CALIBRATION7.1 Channel Offset and Gain CalibrationThe CS5461A provides digital DC offset and gain com-pensation that can b

Seite 30

CS5461A36 DS661F3component present in the system during conversioncommands.7.1.2.2 AC Offset Calibration SequenceCorresponding offset registers IACof

Seite 31 - K1024

CS5461ADS661F3 37ecuted. However, an AC signal should not be used forDC gain calibration.7.1.3.2 DC Gain Calibration SequenceInitiate a DC gain calib

Seite 32

CS5461A38 DS661F38. AUTO-BOOT MODE USING E2PROMWhen the CS5461A MODE pin is asserted (logic 1), theCS5461A auto-boot mode is enabled. In auto-bootmod

Seite 33 - 6.21 Control Register

CS5461ADS661F3 399. BASIC APPLICATION CIRCUITSFigure 15 shows the CS5461A configured to measurepower in a single-phase, 2-wire system while operatingi

Seite 34

CS5461A4 DS661F3LIST OF FIGURESFigure 1. CS5461A Read and Write Timing Diagrams ...

Seite 35 - 7.1.1 Calibration Sequence

CS5461A40 DS661F3VA+ VD+CS5461A0.1 µF470 µF500470 nF500NR3R4RBurden1014VIN+9VIN-IIN-101615IIN+PFMONCPUCLKXOUTXINOptionalClockSourceRESET172124CSSDS

Seite 36 - Reference

CS5461ADS661F3 41VA+ VD+0.1 µF470 µF1k235nF500R1R21014VIN+9VIN-IIN-101615IIN+PFMONCPUCLKXOUTXINOptionalClockSourceRESET172124CSSDISDOSCLKINT0.1 µFV

Seite 37 - 7.3 Active Power Offset

CS5461A42 DS661F310.PACKAGE DIMENSIONSNotes: 3. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold

Seite 38 - 8. AUTO-BOOT MODE USING E

CS5461ADS661F3 4311. ORDERING INFORMATION 12. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION* MSL (Moisture Sensitivity Level) as specifie

Seite 39 - 9. BASIC APPLICATION CIRCUITS

CS5461A44 DS661F313. REVISION HISTORY Revision Date ChangesA1 DEC 2004 Advance ReleasePP1 FEB 2005 Initial Preliminary ReleaseF1 AUG 2005 Final versio

Seite 40 - 40 DS661F3

CS5461ADS661F3 51. OVERVIEWThe CS5461A is a CMOS monolithic power measurement device with a computation engine and an en-ergy-to-frequency pulse outpu

Seite 41 - DS661F3 41

CS5461A6 DS661F32. PIN DESCRIPTIONClock GeneratorCrystal OutCrystal In1,24XOUT, XIN - The output and input of an inverting amplifier. Oscillation occ

Seite 42 - 24L SSOP PACKAGE DRAWING

CS5461ADS661F3 73. CHARACTERISTICS & SPECIFICATIONSRECOMMENDED OPERATING CONDITIONSANALOG CHARACTERISTICS• Min / Max characteristics and specifica

Seite 43 - 11. ORDERING INFORMATION

CS5461A8 DS661F3ANALOG CHARACTERISTICS (Continued)1. Applies when the HPF option is enabled.2. Applies before system calibration.3. All outputs unload

Seite 44 - 13. REVISION HISTORY

CS5461ADS661F3 9DIGITAL CHARACTERISTICS• Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.• Typic

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