Cirrus-logic CS5368 Bedienungsanleitung

Copyright  Cirrus Logic, Inc. 2014(All Rights Reserved)http://www.cirrus.com114 dB, 192 kHz, 8-Channel A/D ConverterFeatures Advanced Multi-bit Delt

10 DS624F5CS53683. CHARACTERISTICS AND SPECIFICATIONSRECOMMENDED OPERATING CONDITIONSGND = 0 V, all voltages with respect to 0 V. 1. TDM Quad-Speed Mo

DS624F5 11CS5368DC POWERMCLK = 12.288 MHz; Master Mode; GND = 0 V. 1. Power-Down is defined as RST = LOW with all clocks and data lines held static at

12 DS624F5CS5368ANALOG CHARACTERISTICS (COMMERCIAL)Test Conditions (unless otherwise specified). VA = 5 V, VD = VLS = VLC 3.3 V, and TA = 25° C. Full

DS624F5 13CS5368ANALOG CHARACTERISTICS (AUTOMOTIVE)Test Conditions (unless otherwise specified). VA = 5.25 to 4.75 V, VD = 5.25 to 3.14 V, VLS = VLC =

14 DS624F5CS5368DIGITAL FILTER CHARACTERISTICSNotes:1. The filter frequency response scales precisely with Fs.2. Response shown is for Fs equal to 48

DS624F5 15CS5368SERIAL AUDIO INTERFACE - I²S/LJ TIMINGThe serial audio port is a three-pin interface consisting of SCLK, LRCK and SDOUT.Logic "0&

16 DS624F5CS5368SERIAL AUDIO INTERFACE - TDM TIMINGThe serial audio port is a three-pin interface consisting of SCLK, LRCK and SDOUT.Logic "0&quo

DS624F5 17CS5368SWITCHING SPECIFICATIONS - CONTROL PORT - I²C TIMINGInputs: Logic 0 = DGND, Logic 1 = VLC, SDA CL=30pFNotes:1. Data must be held for s

18 DS624F5CS5368SWITCHING SPECIFICATIONS - CONTROL PORT - SPI TIMING Inputs: Logic 0 = DGND, Logic 1 = VLC, CDOUT CL=30pFNotes:1. Data must be held fo

DS624F5 19CS53684. APPLICATIONS4.1 PowerCS5368 features five independent power pins that power various functional blocks within the device andallow fo

2 DS624F5CS5368DescriptionThe CS5368 is a complete 8-channel analog-to-digital converter for digital audio systems. It performs sampling, an-alog-to-d

20 DS624F5CS53684.3 Master Clock SourceThe CS5368 requires a Master Clock that can come from one of two sources: an on-chip crystal oscillatordriver o

DS624F5 21CS53684.4 Master and Slave OperationCS5368 operation depends on two clocks that are synchronously derived from MCLK: SCLK and LRCK/FS.See Se

22 DS624F5CS53684.5 Serial Audio Interface (SAI) FormatThe SAI port consists of two timing pins (SCLK, LRCK/FS) and four audio data output pins (SDOUT

DS624F5 23CS53684.5.2 TDM FormatIn TDM Mode, all eight channels of audio data are serially clocked out during a single Frame Sync (FS)cycle, as shown

24 DS624F5CS53684.6.3 Master Mode Clock DividersFigure 13 shows the configuration of the MCLK dividers and the sample rate dividers for Master Mode, i

DS624F5 25CS53684.7 Master and Slave Clock FrequenciesTables 4 through 12 show the clock speeds for sample rates of 48 kHz, 96 kHz and 192 kHz. The MC

26 DS624F5CS5368Table 9. Frequencies for 96 kHz Sample Rate using TDMTable 10. Frequencies for 96 kHz Sample Rate using TDMTable 11. Frequencies for 1

DS624F5 27CS53684.8 ResetThe device should be held in reset until power is applied and all incoming clocks are stable and valid. Uponde-assertion of R

28 DS624F5CS53684.10 Analog ConnectionsThe analog modulator samples the input at half of the internal Master Clock frequency, or 6.144 MHz nom-inally.

DS624F5 29CS53684.11 Optimizing Performance in TDM ModeNoise Management is a design technique that is utilized in the majority of audio A/D converters

DS624F5 3CS5368TABLE OF CONTENTS1. PIN DESCRIPTION ...

30 DS624F5CS53684.13 Control Port OperationThe Control Port is used to read and write the internal device registers. It supports two industry standard

DS624F5 31CS53684.13.2 I²C ModeIn I²C Mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL.There is no C

32 DS624F5CS53685. REGISTER MAPIn Control Port Mode, the bits in these registers are used to control all of the programmable features of the ADC. Allr

DS624F5 33CS5368Bits[5:4] MDIV[1:0] Each bit selects an XTI divider. When either bit is low, an XTI divide-by-1 function isselected. When either bit i

34 DS624F5CS53685.6 04h (HPF) High-Pass Filter Register Default: 0x00, all high-pass filters enabled.The High-Pass Filter Register is used to enable

DS624F5 35CS53685.11 09h Reserved 5.12 0Ah (SDEN) SDOUT Enable Control Register Default: 0x00, all SDOUT pins enabled.The SDOUT Enable Control Regis

36 DS624F5CS53686. FILTER PLOTSFigure 19. SSM PassbandFigure 20. DSM PassbandFigure 21. QSM Passband0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5−

DS624F5 37CS5368Figure 22. SSM StopbandFigure 23. DSM StopbandFigure 24. QSM Stopband0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.91−140−120−100−80−60−40−20

38 DS624F5CS5368Figure 25. SSM -1 dB CutoffFigure 26. DSM -1 dB Cutoff Figure 27. QSM -1 dB Cutoff0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0

DS624F5 39CS53687. PARAMETER DEFINITIONSDynamic RangeThe ratio of the rms value of the signal to the rms sum of all other spectral components over the

4 DS624F5CS53685.3 01h (GCTL) Global Mode Control Register ...325.4

40 DS624F5CS53688. PACKAGE DIMENSIONS THERMAL CHARACTERISTICS INCHES MILLIMETERSDIM MIN NOM MAX MIN NOM MAXA --- 0.055 0.063 --- 1.40 1.60A1 0.002 0.

DS624F5 41CS53689. ORDERING INFORMATION10.REVISION HISTORY Product Description Package Pb-Free Grade Temp Range Container Order #CS5368114dB, 192kHz,

42 DS624F5CS5368 Contacting Cirrus Logic SupportFor all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one

DS624F5 5CS5368LIST OF TABLESTable 1. Power Supply Pin Definitions ...

6 DS624F5CS53681. PIN DESCRIPTIONFigure 1. CS5368 PinoutAIN3+SDOUT1/TDMVLSSDOUT4SDOUT3/TDMGNDSDOUT2M0/SDA/CDOUTAIN5-AIN1+AIN5+AIN6-AIN6+AIN3-AIN7+AIN

DS624F5 7CS5368 Pin Name Pin # Pin DescriptionAIN2+, AIN2-AIN4+, AIN4-AIN3+, AIN3-AIN7+, AIN7-AIN8+, AIN8-AIN6+, AIN6-AIN5+, AIN5-AIN1+, AIN1-1,211,1

8 DS624F5CS5368Control Port ModeCLKMODE 34CLKMODE (Input) - This pin is ignored in Control Port Mode and the same functionality is obtained from the c

DS624F5 9CS53682. TYPICAL CONNECTION DIAGRAM Figure 2. Typical Connection DiagramFor analog buffer configurations, refer to Cirrus Application Note