Cirrus-logic CS4391A Bedienungsanleitung

Preliminary Product InformationThis document contains information for a new product.Cirrus Logic reserves the right to modify this product without not

CS4391A10 DS600PP3SWITCHING CHARACTERISTICS - DSD (Logic 0 = AGND = DGND; Logic 1 = VL) Parameter Symbol Min Typ Max UnitMCLK Duty Cycle 40 50 60 %SC

CS4391ADS600PP3 11SWITCHING CHARACTERISTICS - I2C CONTROL PORT (Inputs: logic 0 = AGND, logic 1 = VL)Notes: 7. Data must be held for sufficient time

CS4391A12 DS600PP3SWITCHING CHARACTERISTICS - SPI CONTROL PORT (Inputs: logic 0 = AGND, logic 1 = VL)Notes: 8. tspi only needed before first falling

CS4391ADS600PP3 132. TYPICAL CONNECTION DIAGRAMSSCLKAudioDataProcessor*External ClockMCLKAGNDAOUTB+CS4391ASDATAVAAOUTB-+5V AnalogModeSelectM1 (SDA/CDI

CS4391A14 DS600PP3DSD_BAudioDataProcessor*External ClockMCLKAGNDAOUTB+CS4391ADSD_AVAAOUTB-+5V AnalogModeSelectM1 (SDA/CDIN)M0 (AD0/CS)AOUTA-AOUTA+VLAn

CS4391ADS600PP3 153. REGISTER QUICK REFERENCE** “default” ==> bit status after power-up-sequence or reset**3.1 MODE CONTROL 1 (ADDRESS 01H)AMUTE (A

CS4391A16 DS600PP33.2 VOLUME AND MIXING CONTROL (ADDRESS 02H)A = B (Channel A Volume = Channel B Volume)Default = ‘0’.0 - AOUTA volume is determined b

CS4391ADS600PP3 173.5 MODE CONTROL 2 (ADDRESS 05H)INVERT_A (Invert Channel A)Default = ‘0’.0 - Disabled1 - EnabledINVERT_B (Invert Channel B)Default

CS4391A18 DS600PP34. REGISTER DESCRIPTION** All register access is R/W in I2C mode and write only in SPI mode **4.1 MODE CONTROL 1 - ADDRESS 01H4.1.1

CS4391ADS600PP3 194.2 VOLUME AND MIXING CONTROL (ADDRESS 02H)4.2.1 Channel A Volume = Channel B Volume (Bit 7)Function:The AOUTA and AOUTB volume leve

CS4391A2 DS600PP3TABLE OF CONTENTS1. CHARACTERISTICS/SPECIFICATIONS ...

CS4391A20 DS600PP34.4 CHANNEL B VOLUME CONTROL - ADDRESS 04H 4.4.1 Mute (Bit 7)Function:The Digital-to-Analog converter output will mute when enable

CS4391ADS600PP3 214.5.5 Freeze (Bit 2)Function:This function allows modifications to the registers without the changes being taking effect until Freez

CS4391A22 DS600PP35. PIN DESCRIPTION - PCM DATA MODEReset - RSTPin 1, InputFunction:Hardware Mode: The device enters a low power mode and the interna

CS4391ADS600PP3 23Serial Clock - SCLKPin 4, InputFunction:Clocks the individual bits of the serial data into the SDATA pin. The required relationship

CS4391A24 DS600PP3Serial Control Interface Clock - SCL/CCLK (Control Port Mode)Pin 8, InputFunction:Clocks the serial control data into or from SDA/C

CS4391ADS600PP3 25Differential Analog Output - AOUTB+, AOUTB- and AOUTA+, AOUTA-Pins 14, 15 and 18, 19, OutputsFunction:The full scale differential an

CS4391A26 DS600PP36. PIN DESCRIPTION - DSD MODEDSD Audio Data - DSD_A and DSD_BPins 3 and 4, InputsFunction:Direct Stream Digital audio data is clocke

CS4391ADS600PP3 27 DIF2 DIF1 DIFO DESCRIPTION0 0 0 Left Justified, up to 24-bit data001I2S, up to 24-bit data0 1 0 Right Justified, 16-bit

CS4391A28 DS600PP3 ATAPI4 ATAPI3 ATAPI2 ATAPI1 ATAPI0 AOUTA AOUTB00000 MUTE MUTE00001 MUTE bR00010 MUTE bL00011 MUTE b[(L+R)/2]00100 aR MUTE00101 aR b

CS4391ADS600PP3 29Note:These clocking ratios are only available inControl Port Mode when the MCLK Divide bit is enabled. Sample Rate(kHz)MCLK (M

CS4391ADS600PP3 35. PIN DESCRIPTION - PCM DATA MODE ... 226. PIN DESCRIP

CS4391A30 DS600PP3M3 M2 M1 M0 DESCRIPTION FORMAT FIGURE1100Left Justified up to 24-bit data071101I2S up to 24-bit data181110Right Justified 16-bit dat

CS4391ADS600PP3 31 Figure 7. Format 0, Left Justified up to 24-Bit DataLRCKSCLKLeft ChannelRight ChannelSDATA +3 +2 +

CS4391A32 DS600PP3LRCKSCLKLeft ChannelRight ChannelSDATA654321098715 14 13 12 11 1010 654321098715 14 13 12 11 1017 16 17 1632 clocks19 18 19 18Figure

CS4391ADS600PP3 337. APPLICATIONS7.1 Recommended Power-up Sequence for Hardware Mode1) Hold RST low until the power supplies, master,and left/right cl

CS4391A34 DS600PP38. CONTROL PORT INTERFACEThe control port is used to load all the internal set-tings of the CS4391A. The operation of the controlpor

CS4391ADS600PP3 35 76543210INCR Reserved Reserved Reserved Reserved MAP2 MAP1 MAP000000000INCR (Auto MAP Increment Enable)Default = ‘0’.0 - D

CS4391A36 DS600PP3-0.25-0.2-0.15-0.1-0.0500.050.10.150.20.250 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5Frequency (normalized to Fs)Amplitude dBFigu

CS4391ADS600PP3 37Figure 24. Double-Speed Transition Band Figure 25. Double-Speed Stopband Rejection

CS4391A38 DS600PP39. PARAMETER DEFINITIONSTotal Harmonic Distortion + Noise (THD+N)The ratio of the rms value of the signal to the rms sum of all othe

CS4391ADS600PP3 3911.PACKAGE DIMENSIONS Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include

CS4391A4 DS600PP3LIST OF FIGURESFigure 1. Serial Mode Input Timing ...

CS4391A40 DS600PP3PACKAGE DIMENSIONS(cont.).INCHES MILLIMETERSDIM MIN NOM MAX MIN NOM MAXA 0.093 0.098 0.104 2.35 2.50 2.65A1 0.004 0.008 0.012 0.10 0

CS4391ADS600PP3 51. CHARACTERISTICS/SPECIFICATIONS (Min/Max performance characteristics and specifications are guaranteed over the Specified Operating

CS4391A6 DS600PP3ANALOG CHARACTERISTICS (Test conditions (unless otherwise specified): Input test signal is a 997 Hz sine wave at 0 dBFS; measurement

CS4391ADS600PP3 7ANALOG CHARACTERISTICS (continued) Notes: 1. Triangular PDF dithered data.2. THD+N specifications for 48 kHz sample rates are made

CS4391A8 DS600PP3DIGITAL CHARACTERISTICS (AGND = 0 V; all voltages with respect to ground.)Parameters Symbol Min Typ Max UnitsHigh-Level Input Voltag

CS4391ADS600PP3 9SWITCHING CHARACTERISTICS - PCM MODES (Inputs: Logic 0 = 0 V, Logic 1 = VL) Notes: 6. This serial clock is available only in Control