Cirrus-logic CS4398 Bedienungsanleitung

Copyright © Cirrus Logic, Inc. 2005(All Rights Reserved)http://www.cirrus.com120 dB, 192 kHz Multi-Bit DAC with Volume ControlFeatures Advanced Multi

10 DS568F1CS4398COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSEThe filter characteristics have been normalized to the sample rate (Fs) and

DS568F1 11CS4398COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE(Continued)DSD COMBINED DIGITAL AND ON-CHIP ANALOG FILTER RESPONSEParameter

12 DS568F1CS4398SWITCHING CHARACTERISTICS(Inputs: Logic 0 = GND, Logic 1 = VLS, CL = 20 pF) Parameters Symbol Min Typ Max UnitsInput Sample Rat

DS568F1 13CS4398 LRCKSCLKLeft ChannelRight ChannelSDATA +3 +2 +1LSB+5 +4MSB-1 -2 -3 -4 -5+3 +2 +1LSB+5 +4MSB-1 -2 -3 -4Figure 3. Format 0 - Left-Just

14 DS568F1CS4398SWITCHING CHARACTERISTICS - DSD(Logic 0 = AGND = DGND; Logic 1 = VLS Volts; CL=20pF) Parameter Symbol Min Typ Max UnitMCLK Duty Cycle

DS568F1 15CS4398SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT (Inputs: Logic 0 = GND, Logic 1 = VLC, CL=20pF)10. Data must be held for suffici

16 DS568F1CS4398SWITCHING CHARACTERISTICS - CONTROL PORT - SPI™ FORMAT (Inputs: Logic 0 = GND, Logic 1 = VLC, CL=20pF)11. tspi only needed before firs

DS568F1 17CS4398DC ELECTRICAL CHARACTERISTICS 16. Normal operation is defined as RST pin = High with a 997 Hz, 0 dBFS input sampled at the highest Fs

18 DS568F1CS4398DIGITAL INTERFACE SPECIFICATIONSParameters Symbol Min Typ Max UnitsInput Leakage Current Iin--±10µAInput Capacitance - 8 - pFHigh-Lev

DS568F1 19CS43983. TYPICAL CONNECTION DIAGRAM Figure 10. Typical Connection Diagram DGND AGNDREF_GNDFILT+VQVD VAVLSVLCMCLKSCLKLRCKSDINDSD_SCLKDSD_A

2 DS568F1CS4398Stand-Alone Mode Features Selectable Oversampling Modes– 32 kHz to 54 kHz Sampling Rates– 50 kHz to 108 kHz Sampling Rates– 100 kHz to

20 DS568F1CS43984. APPLICATIONS4.1 Grounding and Power Supply DecouplingAs with any high resolution converter, the CS4398 requires careful attention t

DS568F1 21CS4398Use of the Mute Control function is not mandatory but recommended for designs requiring the absolute min-imum in extraneous clicks and

22 DS568F1CS4398Table 2. Common Clock Frequencies4.6 Stand-alone Mode SettingsIn Stand-Alone mode (also referred to as “Hardware mode”) the device is

DS568F1 23CS43984.6.1 Recommended Power-up Sequence (Stand-Alone Mode)1. Hold RST low until the power supply, master, and left/right clocks are stable

24 DS568F1CS43984.7.6 Direct Stream Digital (DSD) Mode (Control Port Mode)In Control Port mode, the FM bits (Reg. 02h) are used to configure the devic

DS568F1 25CS43985. CONTROL PORT INTERFACE The Control Port is used to load all the internal settings. The operation of the Control Port may be complet

26 DS568F1CS43985.4.1 Writing in I²C Format To communicate with the CS4398, initiate a START condition of the bus (see Figure 14.). Next, send thechip

DS568F1 27CS4398 Figure 15. Control Port Timing, SPI Format (Write) 5.5.2 Reading in SPIFigure 16 shows the operation of the Control Port in SPI form

28 DS568F1CS43986. REGISTER QUICK REFERENCEAddr Function 7 6 5 4 3 2 1 01h Chip IDPART4 PART3 PART2 PART1 PART0 REV2 REV1 REV0default011 10-- -2h Mode

DS568F1 29CS43987. REGISTER DESCRIPTION** All register access is R/W unless specified otherwise**7.1 Chip ID - Register 01h Function:This register is

DS568F1 3CS4398TABLE OF CONTENTS1. PINOUT DRAWING ...

30 DS568F1CS4398DSD Mode: The relationship between the oversampling ratio of the DSD audio data and the requiredMaster Clock to DSD data rate is defin

DS568F1 31CS43987.3.1 Channel B Volume = Channel A Volume (VOLB=A) Bit 7Function:When set to 0 (default), the AOUTA and AOUTB volume levels are indepe

32 DS568F1CS4398 ATAPI4 ATAPI3 ATAPI2 ATAPI1 ATAPI0 AOUTA AOUTB00000 MUTE MUTE00001 MUTE bR00010 MUTE bL00011 MUTE b[(L+R)/2]00100 aR MUTE00101 aR bR

DS568F1 33CS43987.4 Mute Control - Register 04h 7.4.1 PCM Auto-mute (PAMUTE) Bit 7Function:When set to 1 (default), the Digital-to-Analog converter ou

34 DS568F1CS43987.4.5 MUTE Polarity and DETECT (MUTEP1:0) Bits 1-0Default = 0000 - Auto polarity detect, selected from AMUTEC pin01 - Reserved 10 - Ac

DS568F1 35CS43987.7 Ramp and Filter Control - Register 07h 7.7.1 Soft Ramp AND Zero Cross CONTROL (SZC1:0) Bits 7-6Default = 10Function:Immediate Chan

36 DS568F1CS43987.7.2 Soft Volume Ramp-up after Error (RMP_UP) Bit 5Function:An un-mute will be performed after executing an LRCK/MCLK ratio change or

DS568F1 37CS43987.8 Misc. Control - Register 08h 7.8.1 Power Down (PDN) Bit 7Function:When set to 1 (default), the entire device enters a low-power st

38 DS568F1CS43987.9 Misc. Control - Register 09h 7.9.1 Static DSD Detect (Static_DSD) Bit 3Function:When set to 1 (default), the DSD processor checks

DS568F1 39CS43988. PARAMETER DEFINITIONSTotal Harmonic Distortion + Noise (THD+N)THD+N is the ratio of the rms value of the signal to the rms sum of a

4 DS568F1CS4398LIST OF FIGURESFigure 1. Pinout Drawing...

40 DS568F1CS439810.PACKAGE DIMENSIONS10.1 28-TSSOPFigure 19. 28L TSSOP (4.4 mm Body) Package Drawing Notes:1. “D” and “E1” are reference datums and

DS568F1 41CS439811.APPENDIX 0.4 0.5 0.6 0.7 0.8 0.9 1−120−100−80−60−40−200Frequency(normalized to Fs)Amplitude (dB)0.4 0.42 0.44 0.46 0.48 0.5 0.5

42 DS568F1CS4398 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5−0.02−0.015−0.01−0.00500.0050.010.0150.02Frequency(normalized to Fs)Amplitude (dB)0.4

DS568F1 43CS4398 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1120100806040200Frequency(normalized to Fs)Amplitude (dB)0.2 0.3 0.4 0.5 0.6 0.7 0.8120100806040200

44 DS568F1CS4398 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55109876543210Frequency(normalized to Fs)Amplitude (dB)0 0.05 0.1 0.15 0.2 0.250

DS568F1 45CS4398Table 8. Revision TableRelease Date ChangesA1 November 2002 Initial ReleasePP1 July 2003 -Updated Legal Notice on page 46.-Moved Min/M

46 DS568F1CS4398Contacting Cirrus Logic SupportFor all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one neares

DS568F1 5CS4398LIST OF TABLESTable 1. Clock Ratios ...

6 DS568F1CS43981. PINOUT DRAWING Figure 1. Pinout DrawingDSD_B DSD_ADSD_SCLK VLSSDIN VQSCLK AMUTECLRCK AOUTA-MCLK AOUTA+VD VADGND AGNDM3 (AD1/CDIN) A

DS568F1 7CS4398Pin Name Pin # Pin DescriptionDSD_ADSD_B281Direct Stream Digital Input (Input) - Input for Direct Stream Digital serial audio data.DSD_

8 DS568F1CS43982. CHARACTERISTICS AND SPECIFICATIONS (Min/Max performance characteristics and specifications are guaranteed over the Specified Operati

DS568F1 9CS4398ANALOG CHARACTERISTICS(Test conditions (unless otherwise specified): Input test signal is a 997 Hz sine wave at 0 dBFS; measurement ban