Cirrus-logic CS2100-CP Bedienungsanleitung

Copyright  Cirrus Logic, Inc. 2010(All Rights Reserved)http://www.cirrus.comFractional-N Clock MultiplierFeatures Clock Multiplier / Jitter Reductio

CS2100-CP10 DS840F2CONTROL PORT SWITCHING CHARACTERISTICS - SPI FORMAT Inputs: Logic 0 = GND; Logic 1 = VD; CL=20pF.Notes: 13.tspi is only needed befo

CS2100-CPDS840F2 114. ARCHITECTURE OVERVIEW4.1 Delta-Sigma Fractional-N Frequency SynthesizerThe core of the CS2100 is a Delta-Sigma Fractional-N Freq

CS2100-CP12 DS840F2 Figure 8. Hybrid Analog-Digital PLLNDigital FilterFrequency Comparator forFrac-N GenerationFrequency Reference Clock Delta-Sigma

CS2100-CPDS840F2 135. APPLICATIONS5.1 Timing Reference Clock InputThe low jitter timing reference clock (RefClk) can be provided by either an external

CS2100-CP14 DS840F25.1.2 Crystal Connections (XTI and XTO)An external crystal may be used to generate RefClk. To accomplish this, a 20 pF fundamental

CS2100-CPDS840F2 15Regardless of the setting of the ClkSkipEn bit the PLL output will continue for 223 SysClk cycles (466 msto 1048 ms) after CLK_IN i

CS2100-CP16 DS840F2If CLK_IN is removed and then re-applied within tCS, the ClkSkipEn bit determines whether PLL_OUTcontinues while the PLL re-acquire

CS2100-CPDS840F2 17Typically, applications in which the PLL_OUT signal creates a new clock domain from which all other sys-tem clocks and associated d

CS2100-CP18 DS840F2in either a high resolution (12.20) or high multiplication (20.12) format selectable by the LFRatioCfg bit,with 20.12 being the def

CS2100-CPDS840F2 195.3.3 Effective Ratio (REFF) The Effective Ratio (REFF) is an internal calculation comprised of RUD and the appropriate modifiers,

CS2100-CP2 DS840F2TABLE OF CONTENTS1. PIN DESCRIPTION ...

CS2100-CP20 DS840F25.4 PLL Clock OutputThe PLL clock output pin (CLK_OUT) provides a buffered version of the output of the frequency synthesizer.The d

CS2100-CPDS840F2 215.6 Clock Output Stability Considerations5.6.1 Output SwitchingCS2100 is designed such that re-configuration of the clock routing f

CS2100-CP22 DS840F2The control port operates with either the SPI or I²C interface, with the CS2100 acting as a slave device. SPI Modeis selected if th

CS2100-CPDS840F2 23Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. As shownin Figure 21, the write oper

CS2100-CP24 DS840F26.3 Memory Address PointerThe Memory Address Pointer (MAP) byte comes after the address byte and selects the register to be reador

CS2100-CPDS840F2 258. REGISTER DESCRIPTIONSIn I²C Mode all registers are read/write unless otherwise stated. In SPI mode all registers are write only.

CS2100-CP26 DS840F28.2.3 PLL Clock Output Disable (ClkOutDis)This bit controls the output driver for the CLK_OUT pin. 8.3 Device Configuration 1 (Add

CS2100-CPDS840F2 278.3.3 Enable Device Configuration Registers 1 (EnDevCfg1)This bit, in conjunction with EnDevCfg2, configures the device for control

CS2100-CP28 DS840F28.6 Function Configuration 1 (Address 16h)8.6.1 Clock Skip Enable (ClkSkipEn)This bit enables clock skipping mode for the PLL and a

CS2100-CPDS840F2 298.7 Function Configuration 2 (Address 17h)8.7.1 Enable PLL Clock Output on Unlock (ClkOutUnl)Defines the state of the PLL output du

CS2100-CPDS840F2 38.4.2 Enable Device Configuration Registers 2 (EnDevCfg2) ... 288.5 Ratio (Addr

CS2100-CP30 DS840F29. CALCULATING THE USER DEFINED RATIONote: The software for use with the evaluation kit has built in tools to aid in calculating an

CS2100-CPDS840F2 3110.PACKAGE DIMENSIONSNotes: 1. Reference document: JEDEC MO-1872. D does not include mold flash or protrusions which is 0.15 mm max

CS2100-CP32 DS840F211.ORDERING INFORMATION12.REFERENCES1. Audio Engineering Society AES-12id-2006: “AES Information Document for digital audio measure

CS2100-CP4 DS840F21. PIN DESCRIPTIONPin Name # Pin DescriptionVD 1 Digital Power (Input) - Positive power supply for the digital and analog sections.G

CS2100-CPDS840F2 52. TYPICAL CONNECTION DIAGRAM 21GNDSCL/CCLKSDA/CDIN2 kΩXTI/REF_CLKFrequency Reference CLK_INXTOCLK_OUTAUX_OUT0.1 µFVD+3.3 VNotes:1

CS2100-CP6 DS840F23. CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONSGND = 0 V; all voltages with respect to ground. (Note 1)Notes:

CS2100-CPDS840F2 7AC ELECTRICAL CHARACTERISTICSTest Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; TA = -10°C to +70°C (Commercial Grad

CS2100-CP8 DS840F2PLL PERFORMANCE PLOTSTest Conditions (unless otherwise specified): VD = 3.3 V; TA=25°C; CL=15pF; fCLK_OUT= 12.288 MHz; fCLK_IN= 12.2

CS2100-CPDS840F2 9CONTROL PORT SWITCHING CHARACTERISTICS- I²C FORMATInputs: Logic 0 = GND; Logic 1 = VD; CL=20pF.Notes: 12. Data must be held for suff