Cirrus Logic CS485 Bedienungsanleitung PDF herunterladen (Seite 56)

CS485G Spring 2015 56

(a) Each process gets a uniform linear address space that does not

contain any addresses belonging to any other process or to the

kernel.

(b) The kernel can limit access to parts of that linear address space,

making some execute/read-only (the text), other parts modi-

ﬁable (data, stack), other parts inaccessible (gap between data

and stack).

dress space to save space and loading time.

(d) It is not necessary for all the virtual memory of a process to be

in physical memory for it to run.

3. Cache view of memory

(a) The entire virtual address space of a process is on disk.

(b) The currently active part of the virtual address space is cached

in physical memory.

L2, or L1 caches (closer to the CPU).

(d) The compiler attempts to keep the most heavily used informa-

tion in registers, which are in the CPU itself.

4. MMU tables

(a) Typically the table is a page table.

(b) Virtual memory is chunked into pages, typically 4KB long.

bits long, and a page is 4KB (12 bits) wide, a page table has 2

entries. Each entry contains (x86):

i. Present/missing (1 bit)

ii. Page frame (20 bits, gives page frame number)

iii. Whether the page has been recently accessed (1 bit)

iv. Whether the page has been written and is dirty (1 bit)

v. Does the process have write permission to the page (1 bit)

vi. Does the CPU have access permission in non-privileged mode

(1 bit)

vii. Caching strategy (2 bits)

viii. Normal page size (4KB) or extended (4MB) (1 bit)

ix. TLB caching advice (1 bit)

1 2 ... 51 52 53 54 55 56 57 58 59 60 61 ... 66 67

Keine Kommentare

Cirrus Logic CS485 Bedienungsanleitung Seite 56