Cirrus-logic EP93xx Bedienungsanleitung Seite 444
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11-4 DS785UM1
Copyright 2007 Cirrus Logic
Universal Serial Bus Host Controller
EP93xx User’s Guide
1
1
1
1
11
11.2.2.2 Data Structures
The basic building blocks for communication across the interface are the Endpoint Descriptor
(ED) and Transfer Descriptor (TD).
The Host Controller Driver assigns an Endpoint Descriptor to each endpoint in the system.
The Endpoint Descriptor contains the information necessary for the Host Controller to
communicate with the endpoint. The fields include the maximum packet size, the endpoint
address, the speed of the endpoint, and the direction of data flow. Endpoint Descriptors are
linked in a list.
A queue of Transfer Descriptors is linked to the Endpoint Descriptor for the specific endpoint.
The Transfer Descriptor contains the information necessary to describe the data packets to
be transferred. The fields include data toggle information, shared memory buffer location, and
completion status codes. Each Transfer Descriptor contains information that describes one or
more data packets. The data buffer for each Transfer Descriptor ranges in size from 0 to 8192
bytes with a maximum of one physical page crossing. Transfer Descriptors are linked in a
queue: the first one queued is the first one processed.
Each data transfer type has its own linked list of Endpoint Descriptors to be processed.
Figure 11-3, Typical List Structure, is a representation of the data structure relationships.
Figure 11-3. Typical List Structure
The head pointers to the bulk and control Endpoint Descriptor lists are maintained within the
operational registers in the HC. The Host Controller Driver initializes these pointers prior to
the Host Controller gaining access to them. Should these pointers need to be updated, the
Host Controller Driver may need to halt the Host Controller from processing the specific list,
update the pointer, then re-enable the HC.
The head pointers to the interrupt Endpoint Descriptor lists are maintained within the HCCA.
There is no separate head pointer for isochronous transfers. The first isochronous Endpoint
Descriptor simply links to the last interrupt Endpoint Descriptor. There are 32 interrupt head
pointers. The head pointer used for a particular frame is determined by using the last 5 bits of
the Frame Counter as an offset into the interrupt array within the HCCA.
The interrupt Endpoint Descriptors are organized into a tree structure with the head pointers
being the leaf nodes. The desired polling rate of an Interrupt Endpoint is achieved by
Head Ptr ED
ED
ED
ED
TD
TDTD
TD
TD TD
TD
- EP93xx 1
- Contents 3
- EP93xx User’s Guide 10
- Chapter 21. I 12
- Revision History 22
- Chapter P 23
- 17Preface 23
- P.3 Reference Documents 25
- P.4 Notational Conventions 25
- P.5 Register Example 26
- DS785UM1 P-5 27
- P-6 DS785UM1 28
- Chapter 1 29
- 1Introduction 29
- I-Cache 30
- D-Cache 30
- Memory Management Unit 30
- High-Speed Bus (AHB) 31
- Peripheral Bus (APB) 31
- DS785UM1 1-5 33
- Introduction 33
- 1-6 DS785UM1 34
- 1.4.2 MaverickCrunch 35
- 1.4.3 MaverickKey 36
- DS785UM1 1-9 37
- 1.4.12 Graphics Accelerator 38
- 1.4.13 PCMCIA Interface 38
- Chapter 2 39
- 2.2.2 Block Diagram 40
- 2.2.3 Operations 40
- 2.2.3.1 ARM9TDMI Core 41
- 2-4 DS785UM1 42
- 2.2.3.2.3 MMU Enable 43
- 2.2.3.3.2 Data Cache Enable 44
- DS785UM1 2-7 45
- 2-8 DS785UM1 46
- Figure 2-3. Main Data Paths 46
- 2.2.8 Bus Arbitration 47
- 2.3 AHB Decoder 49
- 2.3.2 AHB-to-APB Bridge 50
- 2.3.3 APB Slave 51
- 2.3.4 Register Definitions 51
- 2.3.5 Memory Map 54
- 2.3.6 Internal Register Map 55
- End Of Line Offset value N 59
- Chapter 3 71
- 3MaverickCrunch Co-Processor 71
- 3-2 DS785UM1 72
- 3.1.3 Pipelines and Latency 73
- 3.1.4 Data Registers 73
- 63 62 55 32 31 0 73
- 3-4 DS785UM1 74
- 3.1.6 Comparisons 76
- 3.2.1 Example 1 78
- 3.2.2 Example 2 79
- 3.3 DSPSC Register 80
- DS785UM1 3-11 81
- 3-12 DS785UM1 82
- DS785UM1 3-13 83
- Immediate pre-indexed 0 91
- Immediate post-indexed 0 91
- Immediate post-indexed 1 91
- 3.5.2 Move Instructions 94
- 3.5.5 Shift Instructions 105
- 3.5.6 Compare Instructions 106
- Description: 117
- Mnemonic: 117
- Bit Definitions: 117
- MaverickCrunch Co-Processor 118
- 3-48 DS785UM1 118
- Copyright 2007 Cirrus Logic 118
- Chapter 4 119
- 4Boot ROM 119
- 4.1.2.1 Image Header 120
- 4.1.2.2 Boot Algorithm 120
- 4.1.2.3 Flowchart 121
- 4.2 Boot Options 122
- CSn[7:6] value: 123
- 4.2.1 UART Boot 124
- 4.2.2 SPI Boot 124
- 4.2.3 FLASH Boot 124
- 5. Set up the SDRAM 126
- 7. Run from SDRAM 126
- Chapter 5 127
- 5System Controller 127
- 5.1.5 Clock Control 130
- DS785UM1 5-5 131
- System Controller 131
- 5-6 DS785UM1 132
- DS785UM1 5-7 133
- 5.1.6 Power Management 135
- 5.1.6.2 System Power States 136
- Power on 137
- Standby Run Halt 137
- 5.1.7 Interrupt Generation 138
- 5.2 Registers 139
- Register Descriptions 140
- PwrSts 140
- Address: 141
- Definition: 141
- Bit Descriptions: 141
- 5-16 DS785UM1 142
- Standby and Halt 143
- DS785UM1 5-19 145
- ClkSet2 146
- DS785UM1 5-21 147
- ScratchReg0, ScratchReg1 148
- APBWait 148
- BusMstrArb 149
- BootModeClr 150
- DeviceCfg 151
- DS785UM1 5-27 153
- 5-28 DS785UM1 154
- VidClkDiv 155
- MIRClkDiv 156
- I2SClkDiv 157
- KeyTchClkDiv 158
- CHIP_ID 159
- Default: 160
- SysSWLock 161
- 5-36 DS785UM1 162
- Chapter 6 163
- 6.1.1 Interrupt Priority 164
- 6.1.3 Interrupt Details 166
- DS785UM1 6-5 167
- Vectored Interrupt Controller 167
- 6-6 DS785UM1 168
- DS785UM1 6-7 169
- 6.2 Registers 170
- from the respective base 170
- VICxIRQStatus 171
- VICxFIQStatus 172
- VICxRawIntr 172
- VICxIntSelect 173
- VICxIntEnable 173
- VICxIntEnClear 174
- VICxSoftInt 174
- VICxSoftIntClear 175
- VICxProtection 175
- VICxVectAddr 176
- VICxVectCntl15 180
- 6-20 DS785UM1 182
- Chapter 7 183
- Timing and Interface 183
- 7.2 Features 185
- 7.3.2 Color Look-Up Tables 186
- Displays 186
- 7.3.7 Hardware Cursor 189
- Interface) 190
- 7.4.2 Video FIFO 191
- 7.4.3 Video Pixel MUX 192
- 7.4.4 Blink Function 192
- 7.4.5 Color Look-Up-Tables 193
- 7.4.6 Color RGB Mux 193
- 7.4.7 Pixel Shift Logic 194
- 7-16 DS785UM1 198
- 7.4.9 Hardware Cursor 206
- 302826242220181614121086420 207
- 1514131211109876543210 207
- 7-26 DS785UM1 208
- DS785UM1 7-27 209
- 7.4.10 Video Timing 210
- DS785UM1 7-29 211
- 7-30 DS785UM1 212
- DS785UM1 7-31 213
- 7.4.11 Blink Logic 214
- 7.4.11.3 Types of Blinking 215
- register with 216
- 888 Blinking: 216
- 7.4.12 Color Mode Definition 217
- 7.5 Registers 218
- No Read/Write 24 bits 218
- VLinesTotal 220
- VSyncStrtStop 220
- VActiveStrtStop 221
- VBlankStrtStop 222
- VClkStrtStop 223
- HClkTotal 224
- HSyncStrtStop 224
- HActiveStrtStop 225
- HBlankStrtStop 226
- HClkStrtStop 227
- VidScrnPage 228
- VidScrnHPage 228
- ScrnLines 229
- LineLength 229
- VLineStep 230
- Address: 0x8003_0230 231
- - Read/Write 231
- Other Video Registers 232
- Brightness 232
- VideoAttribs 233
- 7-52 DS785UM1 234
- DS785UM1 7-53 235
- 7-54 DS785UM1 236
- RasterSWLock 237
- FIFOLevel 238
- PixelMode 239
- ParllIfOut 242
- ParllIfIn 243
- 7-62 DS785UM1 244
- Blink Control Registers 245
- BlinkRate 245
- BlinkMask 245
- BlinkPattrn 246
- PattrnMask 247
- BkgrndOffset 247
- Hardware Cursor Registers 248
- CursorAdrStart 248
- CursorAdrReset 249
- CursorSize 250
- CursorColor1 251
- CursorColor2 251
- CursorBlinkColor1 251
- CursorBlinkColor2 251
- CursorXYLoc 252
- CursorDScanLHYLoc 253
- CursorBlinkRateCtrl 254
- 0x7, 0x15, 0x23, and 0x31 255
- 7-74 DS785UM1 256
- LUTSwCtrl 258
- ColorLUT 259
- Video Signature Registers 259
- VidSigRsltVal 259
- VidSigCtrl 260
- VSigStrtStop 261
- HSigStrtStop 262
- SigClrStr 263
- 7-82 DS785UM1 264
- Chapter 8 265
- 8Graphics Accelerator 265
- 8.2.1 Copy 266
- 8.2.2 Remapping 267
- 8.2.3 Block Fills 267
- 8.5 Register Programming 272
- 8.5.2 Pixel End and Start 273
- 8.5.2.1 4 BPP Word Layout 274
- 8.5.2.2 8 BPP Word Layout 275
- 8.5.2.3 16 BPP WORD Layout 275
- 8.5.2.4 24 BPP mode 276
- 8.6 Register Usage 277
- DS785UM1 8-15 279
- Graphics Accelerator 279
- 8.6.3 Block Fill Function 280
- DS785UM1 8-17 281
- 8.6.4 Block Copy Function 282
- DS785UM1 8-19 283
- 8-20 DS785UM1 284
- Copyright 2007 Cirrus Logic 284
- DS785UM1 8-21 285
- 8.7 Registers 286
- Default: 0x0000_0000 288
- Mask: 0x001F_001F 288
- BLKDESTSTRT 289
- BLKSRCWIDTH 290
- SRCLINELENGTH 290
- BLKDESTWIDTH 291
- BLKDESTHEIGHT 292
- DESTLINELENGTH 293
- 0 0 0 not defined 294
- 0 0 1 4 bit per pixel 294
- 0 1 0 8 bits per pixel 294
- 0 1 1 not defined 295
- 1 0 0 16 bits per pixel 295
- 1 0 1 not defined 295
- 8-32 DS785UM1 296
- DS785UM1 8-33 297
- TRANSPATTRN 298
- BLOCKMASK 298
- BACKGROUND 299
- LINEINC 300
- LINEINIT 300
- LINEPATTRN 301
- 0x000F_FFFF 302
- Chapter 9 303
- 9.1.1.3 Power-down Modes 304
- 9.1.1.4 Address Space 304
- 9.1.2 MAC Engine 305
- 9-4 DS785UM1 306
- 9.1.3.1 Carrier Deference 307
- 9-6 DS785UM1 308
- 9.1.4 Transmit Back-Off 309
- 9.1.4.3 Bit Order 310
- 9.1.4.6 Hash Filter 311
- 9.1.4.7 Flow Control 312
- 9.1.4.8 Receive Flow Control 312
- 9.1.4.11 Accessing the MII 313
- PHY's registers 314
- 9.2 Descriptor Processor 315
- 9-14 DS785UM1 316
- 9.2.3 Receive Status Queue 318
- Receive Status Queue 319
- Receive Status - First Word 320
- DS785UM1 9-19 321
- Receive Status - Second Word 322
- 9.2.3.2 Receive Flow 323
- 9.2.3.3 Receive Errors 324
- DS785UM1 9-23 325
- Receive Descriptor 326
- Receive Status 326
- DS785UM1 9-25 327
- 9-26 DS785UM1 328
- DS785UM1 9-27 329
- 9-30 DS785UM1 332
- DS785UM1 9-31 333
- Transmit Status 334
- DS785UM1 9-33 335
- 9.2.3.12 Transmit Flow 336
- 9.2.3.13 Transmit Errors 337
- 9-36 DS785UM1 338
- 9.2.4 Interrupts 339
- 9.2.5 Initialization 339
- 9.2.5.1 Interrupt Processing 340
- 9.2.5.4 Other Processing 340
- DS785UM1 9-39 341
- 9.3 Registers 342
- 0x8001_0000 - Read/Write 343
- DS785UM1 9-43 345
- Chip Reset: 346
- Soft Reset: 347
- SelfCtl 348
- DS785UM1 9-47 349
- DS785UM1 9-49 351
- 9-50 DS785UM1 352
- 0x0050 through 0x005F 354
- through 005F 354
- 10), is only used as the 355
- HashTbl 356
- TXCollCnt 357
- RXMissCnt 357
- RXRuntCnt 358
- TestCtl 359
- DS785UM1 9-59 361
- IntStsP/IntStsC 362
- DS785UM1 9-61 363
- GlIntSts 364
- GlIntMsk 365
- GlIntROSts 366
- GlIntFrc 366
- DS785UM1 9-65 367
- MIIData 368
- DS785UM1 9-67 369
- 9-68 DS785UM1 370
- DS785UM1 9-69 371
- RXDQBAdd 373
- RXDQBLen 374
- RXDQCurLen 374
- RXDCurAdd 375
- RXBCA 376
- RXStsQBAdd 377
- RXStsQBLen 378
- RXStsQCurLen 378
- RXStsQCurAdd 379
- RXStsEnq 380
- RXHdrLen 380
- TXDQBAdd 381
- TXDQBLen 382
- TXDQCurLen 382
- TXDQCurAdd 383
- TXStsQBAdd 384
- TXStsQBLen 385
- TXStsQCurLen 386
- TXStsQCurAdd 386
- RXBufThrshld 387
- TXBufThrshld 388
- RXStsThrshld 389
- TXStsThrshld 390
- RXDThrshld 391
- TXDThrshld 392
- MaxFrmLen 393
- 9-92 DS785UM1 394
- Chapter 10 395
- 10DMA Controller 395
- 10-2 DS785UM1 396
- DMA Controller 396
- 10.1.3 DMA Operations 397
- 10-4 DS785UM1 398
- DS785UM1 10-5 399
- 10.1.7 Interrupt Interface 400
- DS785UM1 10-7 401
- 10.1.9.1.1 DMA_IDLE 402
- 10.1.9.1.2 DMA_STALL 402
- 10.1.9.1.3 DMA_ON 402
- 10.1.9.1.4 DMA_NEXT 402
- DS785UM1 10-9 403
- 10.1.10.1.1 DMA_IDLE 404
- 10.1.10.1.2 DMA_STALL 404
- 10.1.10.1.3 DMA_MEM_RD 405
- 10.1.10.1.4 DMA_MEM_WR 405
- 10.1.10.1.5 DMA_BWC_WAIT 406
- 10.1.10.2.1 DMA_NO_BUF 406
- 10.1.10.2.2 DMA_BUF_ON 406
- 10.1.10.2.3 DMA_BUF_NEXT 407
- 10-14 DS785UM1 408
- DS785UM1 10-15 409
- 10.1.10.6 Bandwidth Control 410
- 12345678 411
- 10.1.12 Buffer Descriptors 412
- 10.1.13 Bus Arbitration 413
- 10.2 Registers 414
- Register 415
- DS785UM1 10-23 417
- INTERRUPT 419
- DS785UM1 10-27 421
- MAXCNTx 423
- Name Access Bits Reset Value 424
- 10-32 DS785UM1 426
- DS785UM1 10-33 427
- Table 10-9. BWC Decode Values 427
- BWC Bytes 427
- 10-34 DS785UM1 428
- 10-38 DS785UM1 432
- DS785UM1 10-39 433
- 10-40 DS785UM1 434
- SAR_BASEx 436
- DAR_BASEx 437
- SAR_CURRENTx 437
- DAR_CURRENTx 438
- DMAGlInt 438
- Chapter 11 441
- 11.2.1 Data Transfer Types 442
- Device Register 443
- Host Controller 443
- Communications Area 443
- Shared RAM 443
- 11.2.2.2 Data Structures 444
- Interrupt 445
- Pointers 445
- Endpoint Poll Interval (ms) 445
- 11.2.3.3 List Management 447
- 11.2.3.4 Root Hub 447
- 11.2.4.1 USB States 448
- 11.2.4.2 Frame Management 448
- 11.2.4.3 List Processing 448
- 11.2.5.1 AHB Slave 449
- 11.2.5.2 AHB Master 449
- 11.2.5.3 HCI Slave Block 449
- 11.2.5.4 HCI Master Block 450
- 11.2.5.5 USB State Control 450
- 11.2.5.6 Data FIFO 450
- 11.2.5.7 List Processor 450
- 11.3 Registers 451
- HcRevision 452
- HcControl 452
- 11-14 DS785UM1 454
- HcCommandStatus 455
- 11-16 DS785UM1 456
- HcInterruptStatus 457
- HcInterruptEnable 458
- HcInterruptDisable 459
- HcPeriodCurrentED 460
- HcControlHeadED 461
- HcControlCurrentED 462
- HcBulkHeadED 462
- HcBulkCurrentED 463
- HcDoneHead 464
- HcFmInterval 464
- HcFmRemaining 465
- HcFmNumber 466
- HcPeriodicStart 466
- HcLSThreshold 467
- HcRhDescriptorA 468
- HcRhDescriptorB 469
- HcRhStatus 470
- DS785UM1 11-31 471
- HcRhPortStatusx 472
- DS785UM1 11-33 473
- 11-34 DS785UM1 474
- DS785UM1 11-35 475
- USBCfgCtrl 476
- USBHCISts 477
- 11-38 DS785UM1 478
- Chapter 12 479
- 12Static Memory Controller 479
- WAITn must remain asserted 480
- DS785UM1 12-3 481
- Static Memory Controller 481
- 12-4 DS785UM1 482
- DS785UM1 12-7 485
- 12.5 PC Card Memory Mapping 486
- 12.6 Registers 488
- 12-12 DS785UM1 490
- PCAttribute 491
- PCCommon 492
- PCMCIACtrl 494
- DS785UM1 12-17 495
- 12-18 DS785UM1 496
- Chapter 13 497
- 13-2 DS785UM1 498
- 13.3 Address Pin Usage 499
- 13.4 SDRAM Initialization 500
- DS785UM1 13-5 501
- Step Action Reason 501
- 13-6 DS785UM1 502
- 13.6 SDRAM Self Refresh 504
- 1 0 0 0 0 nSDCS3 505
- 0 1 1 1 1 nSDCS3 506
- X 1 1 1 0 nSDCS2 506
- X 1 1 0 1 nSDCS1 506
- X 1 1 0 0 nSDCS0 506
- DS785UM1 13-12 508
- DS785UM1 13-13 509
- DS785UM1 13-14 510
- DS785UM1 13-15 511
- DS785UM1 13-16 512
- 13.9 Registers 513
- GlConfig 514
- DS785UM1 13-19 515
- Default: 0x0000_0080 516
- BootSts 517
- SDRAMDevCfg[3:0] 518
- 13-24 DS785UM1 520
- DS785UM1 13-25 521
- 0 - Width is 32-bits 522
- 1 - Width is 16-bits 522
- Chapter 14 523
- 14.2.1.1 AMBA APB Interface 524
- 14.2.1.2 DMA Block 524
- 14.2.1.3 Register Block 524
- 14-4 DS785UM1 526
- 14.2.2 UART Operation 527
- 14.2.2.1 Error Bits 528
- 14.2.2.2 Disabling the FIFOs 528
- 14.2.3 Interrupts 529
- 14.3 Modem 530
- 14.4 HDLC 530
- 14.4.2 Selecting HDLC Modes 531
- 14.4.3 HDLC Transmit 533
- 14.4.4 HDLC Receive 533
- 14.4.5 CRCs 534
- 14.4.6 Address Matching 534
- 14.4.7 Aborts 535
- 14.4.8 DMA 536
- 14.5.1 Clocking Requirements 537
- 14-16 DS785UM1 538
- 14.1 Registers 539
- UART1RXSts 540
- UART1LinCtrlHigh 541
- UART1LinCtrlMid 542
- UART1LinCtrlLow 543
- UART1Ctrl 544
- UART1Flag 544
- UART1IntIDIntClr 546
- UART1DMACtrl 547
- Modem Register Descriptions 547
- UART1ModemCtrl 547
- UART1ModemSts 548
- HDLC Register Descriptions 549
- UART1HDLCCtrl 549
- 14-28 DS785UM1 550
- DS785UM1 14-29 551
- UART1HDLCAddMtchVal 552
- UART1HDLCAddMask 553
- UART1HDLCRXInfoBuf 553
- UART1HDLCSts 554
- DS785UM1 14-33 555
- 14-34 DS785UM1 556
- DS785UM1 14-35 557
- 14-36 DS785UM1 558
- Chapter 15 559
- 15-2 DS785UM1 560
- 15.2.2 IrDA SIR Operation 561
- 15.2.3 IrDA Data Modulation 562
- 15.3.1 Clocking Requirements 563
- 15-6 DS785UM1 564
- 15.4 Registers 565
- UART2RXSts 566
- UART2LinCtrlHigh 567
- UART2LinCtrlMid 568
- UART2LinCtrlLow 569
- UART2Ctrl 570
- UART2Flag 571
- UART2IntIDIntClr 572
- UART2IrLowPwrCntr 573
- UART2DMACtrl 574
- UART2TMR 575
- 15-18 DS785UM1 576
- Chapter 16 577
- 16UART3 With HDLC Encoder 577
- 16.2.2 Clocking Requirements 578
- 16.3 Registers 579
- UART3RXSts 580
- UART3LinCtrlHigh 581
- UART3LinCtrlMid 583
- UART3LinCtrlLow 583
- UART3Ctrl 584
- UART3Flag 585
- UART3IntIDIntClr 586
- UART3LowPwrCntr 587
- UART3DMACtrl 587
- UART3ModemCtrl 588
- UART3HDLCCtrl 589
- 16-14 DS785UM1 590
- UART3 With HDLC Encoder 590
- DS785UM1 16-15 591
- UART3HDLCAddMtchVal 592
- UART3HDLCAddMask 592
- UART3HDLCRXInfoBuf 593
- UART3HDLCSts 594
- DS785UM1 16-19 595
- 16-20 DS785UM1 596
- Chapter 17 597
- 17.3.1 Overview 598
- 17.3.2.2 Transmitting Data 599
- 17-4 DS785UM1 600
- 8, and if there are three 601
- 17.3.2.3.4 Error Conditions 602
- 17.3.2.4 Special Conditions 603
- 17.4.1 Introduction 604
- 17.4.1.2 Frame Format 605
- 17.4.1.2.1 Address Field 606
- 17.4.1.2.2 Control Field 606
- 17.4.1.2.3 Data Field 606
- 17.4.1.2.4 CRC Field 606
- 17.4.2.2 Receive Operation 607
- 17-12 DS785UM1 608
- 17.4.2.3 Transmit Operation 609
- 17.5.1 Introduction 610
- 17.5.1.2.1 Address Field 612
- 17.5.1.2.2 Control Field 612
- 17.5.1.2.3 Data Field 612
- 17.5.1.2.4 CRC Field 612
- DS785UM1 17-17 613
- 17.5.2.2 Receive Operation 614
- 17.5.2.3 Transmit Operation 615
- 17.5.3 IrDA Connectivity 616
- 17.6 Registers 619
- 17-24 DS785UM1 620
- IrAdrMatchVal 621
- IrDataTail 624
- IrDMACR 626
- 17-38 DS785UM1 634
- Chapter 18 635
- 18Timers 635
- 18.2 Registers 636
- Timer1Load 637
- Timer2Load 637
- Timer3Load 637
- Timer1Value 638
- Timer2Value 638
- Timer3Value 638
- Timer1Clear 639
- Timer2Clear 639
- Timer3Clear 639
- Timer1Control 640
- Timer2Control 640
- Timer3Control 640
- Timer4ValueLow 641
- Timer4ValueHigh 641
- Chapter 19 643
- 19Watchdog Timer 643
- 19.1.1 Watchdog Activation 644
- 19.1.2 Clocking Requirements 644
- 19.1.3 Reset Requirements 644
- 19.1.4 Watchdog Status 644
- 19.1 Registers 645
- 19-4 DS785UM1 646
- Watchdog Timer 646
- WDStatus 647
- 19-6 DS785UM1 648
- Chapter 20 649
- 20-2 DS785UM1 650
- Component 651
- 20.1.1.6 Real-Time Interrupt 651
- 20.1.2 Reset Control 652
- RTCMatch 653
- RTCLoad 654
- RTCCtrl 654
- RTCSWComp 655
- 20-8 DS785UM1 656
- Chapter 21 657
- S Controller 657
- DS785UM1 21-3 659
- 21-4 DS785UM1 660
- S Receiver Channel Overview 661
- 21.3.1 Receiver FIFO’s 662
- S Master Clock Generation 663
- S Bit Clock Rate Generation 665
- 21.6 Interrupts 666
- DS785UM1 21-11 667
- 21.7.1 I 668
- S TX Registers 668
- S TX Register Descriptions 669
- I2STX0Lft 669
- I2STX0Rt 669
- I2STX1Lft 670
- I2STX1Rt 670
- I2STX2Lft 671
- I2STX2Rt 671
- I2STXLinCtrlData 672
- I2STXCtrl 672
- I2STXWrdLen 673
- I2STX0En 673
- I2STX1En 674
- I2STX2En 674
- 21.7.2 I 675
- S RX Registers 675
- I2SRX0Rt 676
- I2SRX1Lft 676
- I2SRX1Rt 677
- I2SRX2Lft 677
- I2SRX2Rt 678
- I2SRXLinCtrlData 678
- I2SRXCtrl 679
- I2SRXWrdLen 679
- I2SRX0En 680
- I2SRX1En 680
- 21.7.3 I 681
- I2STXClkCfg 682
- I2SRXClkCfg 683
- 21-28 DS785UM1 684
- 21.7.4 I 685
- S Global Status Registers 685
- 21-30 DS785UM1 686
- I2SGlCtrl 687
- 21-32 DS785UM1 688
- Chapter 22 689
- 22AC’97 Controller 689
- 22-2 DS785UM1 690
- AC’97 Controller 690
- 22.2.1 Channel Interrupts 691
- 22.2.2 Global Interrupts 692
- 22.3 System Loopback Testing 693
- 22.4 Registers 693
- 22-6 DS785UM1 694
- Address Type Name Description 694
- AC97RXCRx 695
- DS785UM1 22-9 697
- CM RSIZE Data to CPU 697
- AC97TXCRx 698
- DS785UM1 22-11 699
- AC97SRx 700
- AC97RISRx 701
- AC97ISRx 702
- AC97IEx 703
- AC97S1Data 703
- AC97S2Data 704
- AC97S12Data 705
- AC97RGIS 706
- AC97GIS 707
- AC97IM 708
- AC97GCR 709
- AC97Reset 710
- AC97SYNC 711
- AC97GCIS 712
- Chapter 23 713
- 23Synchronous Serial Port 713
- 23.3 SSP Functionality 714
- 23.4 SSP Pin Multiplex 714
- 23.5 Configuring the SSP 714
- 23.5.2 Master/Slave Mode 715
- (1 + scr)) 715
- 23.5.4 Frame Format 715
- 23.5.5 Texas Instruments 716
- 23.5.6 Motorola 717
- SPI Frame Format 717
- 23-6 DS785UM1 718
- Synchronous Serial Port 718
- DS785UM1 23-7 719
- DS785UM1 23-9 721
- Microwire 722
- Frame Format 722
- DS785UM1 23-11 723
- 23-12 DS785UM1 724
- 23.6 Registers 725
- DS785UM1 23-17 729
- SSPCPSR 730
- SSPIIR / SSPICR 730
- 23-20 DS785UM1 732
- Chapter 24 733
- 24Pulse Width Modulator 733
- 24.2.1.1 Example 734
- 24.2.2 Programming Rules 735
- PWMxTermCnt 736
- PWMxDutyCycle 736
- PWMxInvert 737
- Chapter 25 739
- 25-2 DS785UM1 740
- Analog Touch Screen Interface 740
- 25-4 DS785UM1 742
- DS785UM1 25-5 743
- 25-6 DS785UM1 744
- DS785UM1 25-7 745
- 25-8 DS785UM1 746
- DS785UM1 25-9 747
- 25-10 DS785UM1 748
- DS785UM1 25-11 749
- 25.2.3 Direct Operation 750
- 4/8 wire detect Press 751
- 5 wire detect Press 751
- SAMPLE VBAT 752
- DS785UM1 25-15 753
- 25-16 DS785UM1 754
- Signals Function 754
- 25.3 Registers 755
- TSXYMaxMin 757
- TSXYResult 757
- TSSWLock 759
- TSSetup2 760
- DS785UM1 25-23 761
- 25-24 DS785UM1 762
- Chapter 26 763
- 26Keypad Interface 763
- 26.2 Theory of Operation 764
- DS785UM1 26-3 765
- Keypad Interface 765
- 26-4 DS785UM1 766
- 26.2.2 Scan and Debounce 767
- 26.2.3 Interrupt Generation 767
- 26.2.4 Low Power Mode 768
- 26.2.5 Three-key Reset 768
- KeyDiagnostic 770
- Chapter 27 771
- 27IDE Interface 771
- 27.2.2 PIO Operations 773
- 27.2.3 MDMA Operations 774
- 27.2.4 UDMA Operations 775
- 27.2.6 UDMA Example 776
- 27.2.7 DMA Request Latency 777
- DS785UM1 27-9 779
- IDE Interface 779
- Mode MAX IDE Device Bandwidth 779
- 27.3 Registers 780
- IDEMDMAOp 782
- IDEUDMAOp 782
- IDEDataOut 783
- IDEDataIn 784
- IDEMDMADataOut 784
- IDEMDMADataIn 785
- IDEUDMADataOut 785
- IDEUDMADataIn 786
- IDEUDMASts 786
- IDEUDMADebug 788
- IDEUDMAWrBufSts 788
- IDEUDMARdBufSts 789
- 27-20 DS785UM1 790
- Chapter 28 791
- 28GPIO Interface 791
- 28.1.1 Memory Map 793
- 28-4 DS785UM1 794
- GPIO Interface 794
- (Ports C, D, E, G, H) 794
- 28.1.3 Reset 795
- 28.1.4 GPIO Pin Map 796
- 28.2 Registers 799
- PxDDR 801
- GPIOxIntEn 802
- GPIOxIntType1 802
- GPIOxIntType2 803
- GPIOxEOI 804
- GPIOxDB 804
- RawIntStsX 805
- IntStsX 805
- EEDrive 806
- 28-18 DS785UM1 808
- Chapter 29 809
- 29Security 809
- 29.4 Registers 810
- Chapter 30 811
- 30Glossary 811
- Chapter 31 813
- 31EP93XX Register List 813
- 31-2 DS785UM1 814
- EP93XX Register List 814
- Register Name Page Number 814
- DS785UM1 31-3 815
- 31-4 DS785UM1 816
- DS785UM1 31-5 817
- 31-6 DS785UM1 818
- DS785UM1 31-7 819
- 31-8 DS785UM1 820
- DS785UM1 31-9 821
- 31-10 DS785UM1 822
- DS785UM1 31-11 823
- 31-12 DS785UM1 824
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