Figure 6. Typical Connection Diagram, Master and Slave Modes
* The connection (VL or GND) and value of these three resistors determines the mode of operation for the input
and output serial ports as described in Table 1 Serial Audio Port Master/Slave and Clock Ratio Select Start-Up Op-
tions (MS_SEL), and Table 2, “Serial Audio Input Port Start-Up Options (SAIF),” on page 18 and Table 3, “Serial
Audio Output Port Start-Up Options (SAOF),” on page 18.
** MCLK_OUT pin should be pulled high through a 47 k
resistor if an MCLK output is not needed.
*** This pin must not be pulled high. See Section 1, “Pin Descriptions.”
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