Cirrus-logic CS44800 Bedienungsanleitung

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Copyright © Cirrus Logic, Inc. 2006
(All Rights Reserved)
http://www.cirrus.com
8-Channel Digital Amplifier Controller
Features
> 100 dB Dynamic Range - System Level
< 0.03% THD+N @ 1 W - System Level
32 kHz to 192 kHz Sample Rates
Internal Oscillator Circuit Supports 24.576 MHz
to 54 MHz Crystals
Integrated Sample Rate Converter (SRC)
Eliminates Clock Jitter Effects
Input Sample Rate Independent Operation
Power Supply Rejection Realtime Feedback
Spread Spectrum Modulation - Reduces EMI
PWM Popguard
®
for Single-Ended Mode
Eliminates AM Frequency Interference
Programmable Load Compensation Filters
Support for up to 40 kHz Audio Bandwidth
Digital Volume Control with Soft Ramp
+24 to -127 dB in 0.25 dB Steps
Per Channel Programmable Peak Detect and
Limiter
SPI™ and I²C
®
Host Control Interfaces
Separate 2.5 V to 5.0 V Serial Port and Host
Control Port Supplies
DAI
Serial
Port
XTAL
PWMOUTA1+
Power
Supply
Rejection
PWMOUTB1+
SPI/I
2
C Host
Control Port
SCL/CCLK
AD1/CDIN
AD0/CS
RST
INT
PSR_MCLK
PSR_SYNC
PSR_DATA
PWM
Backend
Control/
Status
GPIO4
GPIO5
GPIO0
GPIO1
GPIO2
XTO
XTI
PWMOUTA1-
PWMOUTB1-
PWMOUTA2+
PWMOUTB2+
PWMOUTA2-
PWMOUTB2-
PWMOUTA3+
PWMOUTB3+
PWMOUTA3-
PWMOUTB3-
MUTE
PWMOUTA4+
PWMOUTB4+
PWMOUTA4-
PWMOUTB4-
DAI_MCLK
DAI_SCLK
DAI_LRCK
DAI_SDIN1
DAI_SDIN2
DAI_SDIN3
DAI_SDIN4
Volume
/ Limiter
Multibit
Σ∆
Modulator
PWM
Conversion
PWM
Conversion
PWM
Conversion
PWM
Conversion
Volume
/ Limiter
Multibit
Σ∆
Modulator
Volume
/ Limiter
Multibit
Σ∆
Modulator
Volume
/ Limiter
Multibit
Σ∆
Modulator
PWM
Clock
Control
Auto Fs
Detect
GPIO3
GPIO6
PSR_EN
PSR_RESET
PS_SYNC
SRC
SYS_CLK
SDA/CDOUT
MARCH '06
DS632F1
CS44800
Seitenansicht 0
1 2 3 4 5 6 ... 79 80

Inhaltsverzeichnis

Seite 1 - Features

Copyright © Cirrus Logic, Inc. 2006(All Rights Reserved)http://www.cirrus.com8-Channel Digital Amplifier ControllerFeatures > 100 dB Dynamic Range

Seite 2 - General Description

10 DS632F1CS44800PWM OUTPUT PERFORMANCE CHARACTERISTICS (Logic “0” = GND = 0 V; Logic “1” = VLS = VLC; VD = 2.5 V; DAI_MCLK = 12.288 MHz; XTAL= 24.576

Seite 3 - TABLE OF CONTENTS

DS632F1 11CS44800PWM FILTER CHARACTERISTICS (Logic “0” = GND = 0 V; Logic “1” = VLS = VLC; VD = 2.5 V; DAI_MCLK = 12.288 MHz; XTAL = 24.576 MHz; PWM

Seite 4

12 DS632F1CS44800SWITCHING CHARACTERISTICS - SYS_CLK(VD = 2.5 V, VDP = VLC = VDX = 3.3 V, VLS = 2.5 V to 5.0 V, Cload = 50 pF) SWITCHING CHARACTERISTI

Seite 5

DS632F1 13CS44800SWITCHING CHARACTERISTICS - DAI INTERFACE(VD = 2.5 V, VDX = VDP = VLC = 3.3 V, VLS = 2.5 V to 5.0 V; Inputs: Logic 0 = GND, Logic 1 =

Seite 6 - LIST OF FIGURES

14 DS632F1CS44800SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT(VD = 2.5 V, VDX = VDP = VLS = 3.3 V; VLC = 2.5 V to 5.0 V; Inputs: Logic 0 = GN

Seite 7 - LIST OF TABLES

DS632F1 15CS44800SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT (VD = 2.5 V, VDP = VLS = 3.3 V; VLC = 2.5 V to 5.0 V; Inputs: Logic 0 = GND, Lo

Seite 8 - ABSOLUTE MAXIMUM RATINGS

16 DS632F1CS448002. PIN DESCRIPTIONS Pin Name Pin # Pin DescriptionFigure 10. CS44800 Pinout DiagramGNDXTIXTOVLSDAI_MCLKDAI_SCLKSCL/CCLKSDA/CDOUTAD1/

Seite 9 - DC ELECTRICAL CHARACTERISTICS

DS632F1 17CS44800PS_SYNC 3Power Supply Synchronization Clock (Output) - The PWM synchronized clock to the switch mode power supply. XTI 5Crystal

Seite 10 - PWMOUTxx

18 DS632F1CS44800GPIO2 33General Purpose Input, Output (Input/Output) - This pin is configured as an input follow-ing a RST condition. It can be confi

Seite 11 - PWM FILTER CHARACTERISTICS

DS632F1 19CS44800GND1, 4, 18, 28, 36, 42, 48, 53, 59Digital Ground (Input) - Ground reference for digital circuits.

Seite 12 - Figure 5. PS_SYNC Timings

2 DS632F1CS44800General DescriptionThe CS44800 is a multi-channel digital-to-PWM Class D audio system controller including interpolation, sample ratec

Seite 13

20 DS632F1CS448002.1 I/O Pin Characteristics Signal NamePower Rail I/O Driver ReceiverRST VLC Input - 2.5 V and 3.3/5.0 V TTL Compatible.SCL/CCLK

Seite 14

DS632F1 21CS448003. TYPICAL CONNECTION DIAGRAMS PWMOUTA1+PWMOUTA1-PWMOUTB1+PWMOUTB1-GNDPWM IN1OUT1CONTROLPWMOUTA2+PWMOUTA2-PWMOUTB2+PWMOUTB

Seite 15

22 DS632F1CS44800GNDPSR_DATAPSR_SYNCPSR_MCLKCS4461ADCPower Supply RailPSR_RESETPSR_ENPS_SYNCPower Supply Sync ClockOptionalPWMOUTA1+PWMOUTA1-PWMOUTB1+

Seite 16 - 2. PIN DESCRIPTIONS

DS632F1 23CS448004. APPLICATIONS4.1 OverviewThe CS44800 is a multi-channel digital-to-PWM Class D audio system controller including interpolation,samp

Seite 17

24 DS632F1CS44800• Digital volume control with soft ramp.• Individual channel volume gain, attenuation and mute capability; +24 to -127 dB in 0.25 dB

Seite 18

DS632F1 25CS448004.3.1 FsIn Domain ClockingCommon DAI_MCLK frequencies and sample rates are shown in Table 1. 4.3.2 FsOut Domain ClockingTo ensure the

Seite 19

26 DS632F1CS44800 Appropriate clock dividers for each functional block and a programmable divider to support an output forswitched-mode power supp

Seite 20

DS632F1 27CS448004.4 FsIn Clock Domain Modules4.4.1 Digital Audio Input PortThe CS44800 interfaces to an external Digital Audio Processor via the Digi

Seite 21 - DS632F1 21

28 DS632F1CS448004.4.1.1 I²S Data FormatFor I²S, data is received most significant bit first, one DAI_SCLK delay after the transition of DAI_LRCK,and

Seite 22 - 22 DS632F1

DS632F1 29CS448004.4.1.3 Right-Justified Data Format In the right-justified format, data is received most significant bit first and with the least sig

Seite 23 - 4. APPLICATIONS

DS632F1 3CS44800TABLE OF CONTENTS1. CHARACTERISTICS AND SPECIFICATIONS ...

Seite 24 - Additional Features

30 DS632F1CS448004.4.1.5 One Line Mode #2 In One Line mode #2 format, data is received most significant bit first on the first DAI_SCLK after aDAI_LRC

Seite 25 - 4.3.2 FsOut Domain Clocking

DS632F1 31CS448004.4.2 Auto Rate DetectThe CS44800 will automatically determine the incoming sample rate, DAI_LRCK, to master clock,DAI_MCLK, ratio an

Seite 26 - 26 DS632F1

32 DS632F1CS448004.5 FsOut Clock Domain Modules4.5.1 Sample Rate ConverterOne of the characteristics of a PWM amplifier is that the frequency content

Seite 27 - 4.4 FsIn Clock Domain Modules

DS632F1 33CS44800ger (addresses 09h - 10h)” on page 58. Volume control changes are programmable to ramp in incrementsof 0.125 dB at a variable rate co

Seite 28 - 4.4.1.1 I²S Data Format

34 DS632F1CS44800 4.5.6 Interpolation FilterThe times 2 (2x) interpolation filter is part of the Quantizer and is used to up sample the data to suppo

Seite 29 - 4.4.1.4 One Line Mode #1

DS632F1 35CS448004.5.10 Power Supply Rejection (PSR) Real-Time FeedbackInherent to most Class D power amplifier solutions is the requirement for a cle

Seite 30 - 4.4.1.6 TDM Mode

36 DS632F1CS448004.6 Control Port Description and TimingThe control port is used to access the registers, allowing the CS44800 to be configured for th

Seite 31 - 4.4.3 De-Emphasis

DS632F1 37CS448004.6.2 I²C ModeIn I²C mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL.There is no C

Seite 32 - 4.5.1 Sample Rate Converter

38 DS632F1CS44800Receive acknowledge bit. Receive byte, contents of selected register. Send acknowledge bit. Send stop condition. Each byte is separat

Seite 33 - Features:

DS632F1 39CS448005. POWER SUPPLY, GROUNDING, AND PCB LAYOUTThe CS44800 requires a 2.5 V digital power supply for the core logic. In order to support a

Seite 34 - 4.5.9 PWM Outputs

4 DS632F1CS448007.1.1 Increment (INCR) ...

Seite 35

40 DS632F1CS44800Figure 28 shows the recommended crystal circuit layout. U1 is the CS44800. C1 and C2 are the VDX power supplydecoupling capacitors. Y

Seite 36 - 4.6.1 SPI Mode

DS632F1 41CS44800Figure 29 shows the recommended PSR circuit layout. See the CS4461 datasheet for further details on the inputbuffer and other associa

Seite 37 - 4.6.2 I²C Mode

42 DS632F1CS448005.1 Reset and Power-UpReliable power-up can be accomplished by keeping the device in reset until the power supplies, clocks, andconfi

Seite 38 - 4.6.4 Host Interrupt

DS632F1 43CS448006. When driving a single-ended (half-bridged) power output stage, set the RAMP[1:0] bits to ‘11’b and the required ramp speed, to ini

Seite 39

44 DS632F1CS44800 5.1.4 Recommended Power-Down Sequence1. Mute all channel outputs by setting the corresponding CHxx_MUTE bits to ‘1’b. 2. When drivin

Seite 40

DS632F1 45CS448008. Set the PDN bit to ‘1’b to put the CS44800 in the power down state.

Seite 41

46 DS632F1CS448006. REGISTER QUICK REFERENCEAddr Function 7 6 5 4 3 2 1 001h ID / Rev. CHIP_ID3 CHIP_ID2 CHIP_ID1 CHIP_ID0 REV_ID3 REV_ID2 REV_ID1 REV

Seite 42 - Transient Control

DS632F1 47CS4480011hChannel Vol. Con-trol 1-FractionCHB2_FVOL1 CHB2_FVOL0 CHA2_FVOL1 CHA2_FVOL0 CHB1_FVOL1 CHB1_FVOL0 CHA1_FVOL1 CHA1_FVOL0page 59

Seite 43

48 DS632F1CS4480021hChnl A3 Comp. Filter - Fine AdjRESERVED RESERVED CHA3_FINE5 CHA3_FINE4 CHA3_FINE3 CHA3_FINE2 CHA3_FINE1 CHA3_FINE0page 63 default

Seite 44

DS632F1 49CS4480031hPWM Config OSRATE RESERVED RESERVED A1/B1_OUT_CNFG A2/B2_OUT_CNFG A3_OUT_CNFG B3_OUT_CNFG A4/B4_ OUT_CNFGpage 68 default 0 0

Seite 45 - DS632F1 45

DS632F1 5CS448007.19.1 Channel Compensation Filter - Fine Adjust (CHXX_FINE[5:0]) ... 637.20 Interrupt Mode Con

Seite 46 - 6. REGISTER QUICK REFERENCE

50 DS632F1CS448007. REGISTER DESCRIPTIONAll registers are read/write except for I.D. and Revision Register, Interrupt Status and Decimator OutD regist

Seite 47 - DS632F1 47

DS632F1 51CS448007.3 Clock Configuration and Power Control (address 02h)7.3.1 Enable SYS_CLK Output (EN_SYS_CLK)Default = 1 Function:This bit enables

Seite 48 - 48 DS632F1

52 DS632F1CS448007.3.5 Power Down Output Mode (PDN_OUTPUT_MODE)Default = 00 - PWM Outputs are driven low during power down1 - PWM Outputs are driven t

Seite 49 - DS632F1 49

DS632F1 53CS448007.5 Misc. Configuration (address 04h)7.5.1 Digital Interface Format (DIFX)Default = 001Function:These bits select the digital interfa

Seite 50 - 7. REGISTER DESCRIPTION

54 DS632F1CS448007.5.4 De-Emphasis Control (DEM[1:0])Default = 0000 - no de-emphasis01 - 32 kHz de-emphasis filter 10 - 44.1 kHz de-emphasis filter11

Seite 51 - 76 5 4 3 2 10

DS632F1 55CS448007.7 Volume Control Configuration (address 06h)7.7.1 Single Volume Control (SNGVOL)Default = 0Function:The individual channel volume l

Seite 52 - 7.3.6 Power Down (PDN)

56 DS632F1CS44800trol changes, by the Soft and Zero Cross bits (SZC[1:0]). This bit does not cause a mute condition to occur.The MUTE_50/50 bit only d

Seite 53 - 7654 3210

DS632F1 57CS448007.8 Master Volume Control - Integer (address 07h)7.8.1 Master Volume Control - Integer (MSTR_IVOL[7:0])Default = 00000000Function:The

Seite 54 - 76543210

58 DS632F1CS448001. Convert the decimal integer to binary. This is MSTR_IVOL[7:0]. 2. Select the bit representation of the desired 0.25 fractional inc

Seite 55

DS632F1 59CS448007.10 Channel XX Volume Control - Integer (addresses 09h - 10h)7.10.1 Channel Volume Control - Integer (CHXx_IVOL[7:0])Default = 00000

Seite 56 - 7.7.6 Auto-Mute (AMUTE)

6 DS632F1CS44800LIST OF FIGURESFigure 1.Performance Characteristics Evaluation Active Filter Circuit ...

Seite 57

60 DS632F1CS44800 7.13 Channel Mute (address 13h)7.13.1 Independent Channel Mute (CHXX_MUTE)Default = 00 - Disabled1 - EnabledFunction:The PWM outputs

Seite 58

DS632F1 61CS448007.15 Peak Limiter Control Register (address 15h) 7.15.1 Peak Signal Limit All Channels (LIMIT_ALL)Default = 00 - individual channel 1

Seite 59 - in the Channel Vol

62 DS632F1CS44800 7.17 Limiter Release Rate (address 17h) 7.17.1 Release Rate (RRATE[7:0])Default = 00100000Function:The limiter release rate is us

Seite 60

DS632F1 63CS448007.19 Chnl XX Load Compensation Filter - Fine Adjust (addresses 19h, 1Bh, 1Dh, 1Fh, 21h, 23h, 25h, 27h)7.19.1 Channel Compensation Fil

Seite 61

64 DS632F1CS448007.20.2 Overflow Level/Edge Select (OVFL_L/E)Default = 0Function:This bit defines the OVFL interrupt type (0 = level sensitive, 1 = ed

Seite 62

DS632F1 65CS448007.22.2 SRC Lock Interrupt (SRC_LOCK)Default = 0Function:When high, indicates that on all active channels, the sample rate converters

Seite 63

66 DS632F1CS448007.23 Channel Over Flow Status (address 2Bh) (Read Only)For all bits in this register, a ‘1’ means the associated condition has occurr

Seite 64 - 7 6 5 4 3210

DS632F1 67CS448007.26 GPIO Pin Level/Edge Trigger (address 2Eh)7.26.1 GPIO Level/Edge Input Sensitive (GPIOX_L/E)Default = 0Function:General Purpose I

Seite 65

68 DS632F1CS448007.28 GPIO Interrupt Mask Register (address 30h)7.28.1 GPIO Pin Interrupt Mask (M_GPIOX)Default = 0Function:General Purpose Input - Th

Seite 66

DS632F1 69CS44800er-down state by setting the PDN bit in the register “Clock Configuration and Power Control (address 02h)”on page 51 to a 1b. Attempt

Seite 67 - 76 543210

DS632F1 7CS44800LIST OF TABLESTable 1. Common DAI_MCLK Frequencies ...

Seite 68 - 76 5 4 3 2 1 0

70 DS632F1CS44800state by setting the PDN bit in the register “Clock Configuration and Power Control (address 02h)” onpage 51 to a 1b. Attempts to wri

Seite 69

DS632F1 71CS44800The Channel Delay bits allow delay adjustment of each of the PWMOUT differential signal pairs, PW-MOUTAx+/PWMOUTAx- from the associat

Seite 70

72 DS632F1CS44800 PWMOUTA2+PWMOUTA2-PWMOUTB2+PWMOUTB2-tchdlytdifdlytdifdlyPWMOUTA1+PWMOUTA1-PWMOUTB1+PWMOUTB1-tchdlytdifdlytdifdlyPWMOUTA3+PWMOUTA3-

Seite 71

DS632F1 73CS448007.32 PSR and Power Supply Configuration (address 34h)7.32.1 Power Supply Rejection Enable (PSR_EN)Default = 00 - disable1 - enableFun

Seite 72 - Figure 31. PWM Output Delay

74 DS632F1CS448007.32.2 Power Supply Rejection Reset (PSR_RESET)Default = 00 - force reset condition1 - remove reset conditionFunction:This bit is use

Seite 73

DS632F1 75CS448007.33.2 Decimator Scale (DEC_SCALE[18:0])Default = 25868hFunction:These bits are used to scale the power supply reading (Decimator Out

Seite 74

76 DS632F1CS448008. PARAMETER DEFINITIONSDynamic Range (DR)The ratio of the rms value of the signal to the rms sum of all other spectral components ov

Seite 75

DS632F1 77CS44800Signal to Noise Ratio (SNR)SNR, similar to DR, is the ratio of an arbitrary sinusoidal input signal to the RMS sum of the noise floor

Seite 76 - 8. PARAMETER DEFINITIONS

78 DS632F1CS4480010.PACKAGE DIMENSIONS INCHES MILLIMETERSDIM MIN NOM MAX MIN NOM MAXA --- 0.55 0.063 --- 1.40 1.60A1 0.002 0.004 0.006 0.05

Seite 77 - 9. REFERENCES

DS632F1 79CS4480011.THERMAL CHARACTERISTICS12.ORDERING INFORMATION 13.REVISION HISTORY Parameter Symbol Min Typ Max UnitsJunction to Ambient Thermal I

Seite 78 - 64L LQFP PACKAGE DRAWING

8 DS632F1CS448001. CHARACTERISTICS AND SPECIFICATIONS(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Condi

Seite 79 - 13.REVISION HISTORY

80 DS632F1CS44800Contacting Cirrus Logic SupportFor all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one

Seite 80

DS632F1 9CS44800DC ELECTRICAL CHARACTERISTICS(GND = 0 V, all voltages with respect to ground; DAI_MCLK = 12.288 MHz, XTAL = 24.576 MHz, PWM Switch Rat

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