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Copyright © Cirrus Logic, Inc. 2008
(All Rights Reserved)
www.cirrus.com
CDB5376
Multichannel Seismic Evaluation System
Features
z Four-channel Seismic Acquisition Node
CS3301A geophone amplifiers (2x)
CS3302A hydrophone amplifiers (2x)
CS5372A dual ∆Σ modulators (2x)
CS5376A quad digital filter (1x)
CS4373A ∆Σ test DAC (1x)
Precision voltage reference
Clock recovery PLL
z On-board Microcontroller
SPI™ interface to digital filter
USB communication with PC
z PC Evaluation Software
Register setup & control
FFT frequency analysis
Time domain analysis
Noise histogram analysis
General Description
The CDB5376 board is used to evaluate the functionality
and performance of the Cirrus Logic multichannel seis-
mic chip set. Data sheets for the CS3301A, CS3302A,
CS4373A, CS5371A/72A, and CS5376A devices should
be consulted when using the CDB5376 evaluation
board.
Screw terminals connect external differential geophone
or hydrophone sensors to the analog inputs of the mea-
surement channels. An on-board test DAC creates
precision differential analog signals for in-circuit perfor-
mance testing without an external signal source.
The evaluation board includes an 8051-type microcon-
troller with hardware SPI
and USB serial interfaces.
The microcontroller communicates with the digital filter
via SPI and with the PC evaluation software via USB.
The PC software controls register and coefficient initial-
ization and performs time domain, histogram, and FFT
frequency analysis on captured data.
ORDERING INFORMATION
CDB5376 Evaluation Board
JAN ‘08
DS612DB3
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1 2 3 4 5 6 ... 79 80

Inhaltsverzeichnis

Seite 1 - General Description

Copyright © Cirrus Logic, Inc. 2008(All Rights Reserved)www.cirrus.comCDB5376Multichannel Seismic Evaluation SystemFeaturesz Four-channel Seismic Acqu

Seite 2 - REVISION HISTORY

CDB537610 DS612DB31.2.2 Default DIP Switch Settings Table 5. RS-485 Default Jumper Settings J14I2C ClockSCL+ 1 ---------- 2SCL- 3 ---------- 4SCL 5 **

Seite 3 - TABLE OF CONTENTS

CDB5376DS612DB3 111.3 Software Setup1.3.1 PC RequirementsThe PC hardware requirements for the Cirrus Seismic Evaluation system are:• Windows XP®, Wind

Seite 4

CDB537612 DS612DB3CDB5376 as an unknown USB device.• If prompted for a USB driver, skip to the next step. If not, using Windows Hardware Device Manage

Seite 5 - LIST OF FIGURES

CDB5376DS612DB3 131.4 Self-testing CDB5376Noise and distortion self-tests can be performed once hardware and software setup are complete.First, initia

Seite 6 - LIST OF TABLES

CDB537614 DS612DB3• Once the Setup panel is set, select Configure on the Digital Filter sub-panel.• After digital filter configuration is complete, cl

Seite 7 - 1.2 Hardware Setup

CDB5376DS612DB3 152. HARDWARE DESCRIPTION2.1 Block Diagram Major blocks of the CDB5376 evaluation board include:• CS3301A Geophone Amplifier (2x)• CS3

Seite 8 - 1.2.1 Default Jumper Settings

CDB537616 DS612DB32.2 Analog Hardware2.2.1 Analog Inputs2.2.1.1 External Inputs - INA, INB, BNCExternal signals into CDB5376 are from two major classe

Seite 9

CDB5376DS612DB3 172.2.1.3 Internal Inputs - DAC_OUT, DAC_BUFThe CS4373A test DAC has two high-performance differential test outputs, a precision outpu

Seite 10

CDB537618 DS612DB32.2.1.6 Common Mode BiasDifferential analog signals into the CS3301A/02A amplifiers are required to be biased to the center of thepo

Seite 11 - DS612DB3 11

CDB5376DS612DB3 192.2.2 Differential AmplifiersThe CS3301A/02A amplifiers act as a low-noise gain stage for internal or external differential analog s

Seite 12 - 12 DS612DB3

CDB53762 DS612DB3REVISION HISTORY Revision Date ChangesDB1 FEB 2006 Initial release.DB2 MAR 2006 Added USB support.DB3 DEC 2007Updated schematics:CS33

Seite 13 - 1.4.1 Noise test

CDB537620 DS612DB32.2.2.3 Anti-alias RC FiltersThe CS5372A ∆Σ modulator is 4th order and high-frequency input signals can cause instability. Simplesin

Seite 14 - 1.4.2 Distortion Test

CDB5376DS612DB3 212.2.3.2 Offset Enable - OFSTThe CS5372A ∆Σ modulator requires differential offset to be enabled to eliminate idle tones for a termi-

Seite 15 - DS612DB3 15

CDB537622 DS612DB32.2.5 Voltage ReferenceA voltage reference on CDB5376 creates a precision voltage from the regulated analog supplies for themodulato

Seite 16 - 2.2 Analog Hardware

CDB5376DS612DB3 232.3 Digital Hardware2.3.1 Digital FilterThe CS5376A quad digital filter performs filtering and decimation of four delta-sigma bit st

Seite 17 - 2.2.1.5 Input RC Filters

CDB537624 DS612DB3Modulator ∆Σ data is input through the modulator interface.Test DAC ∆Σ data is generated by the test bit stream generator.Amplifier,

Seite 18 - 2.2.1.6 Common Mode Bias

CDB5376DS612DB3 252.3.1.1 MCLK Conversion to ACLKThe CS5376A digital filter creates the analog sampling clock used by the CS5372A ∆Σ modulators andCS4

Seite 19 - DS612DB3 19

CDB537626 DS612DB3output sync, reset;///////////////////////// signal assignments///////////////////////assign sck = ssi_mc? 1'bz:sck_mc;assign

Seite 20 - 2.2.2.3 Anti-alias RC Filters

CDB5376DS612DB3 272.3.3 Digital Control SignalsThe reset, synchronization, and timebreak signals to the CS5376A digital filter can be generated by pus

Seite 21 - 2.2.3.2 Offset Enable - OFST

CDB537628 DS612DB3Pin # Pin Name Assignment Description 1 P0.1 SDTKI_MC Token to start CS5376A data transaction 2 P0.0 SYNC_IO SYNC signal from

Seite 22 - 2.2.5.2 Common Mode Bias

CDB5376DS612DB3 29Many connections to the C8051F320 microcontroller are inactive by default, but are provided for conve-nience during custom reprogram

Seite 23 - 2.3.1 Digital Filter

CDB5376DS612DB3 3TABLE OF CONTENTS1. INITIAL SETUP ...

Seite 24 - 24 DS612DB3

CDB537630 DS612DB3input on CDB5376 can receive a lower-frequency system clock and create a synchronous higher-frequen-cy clock using an on-board PLL.

Seite 25 - 2.3.2 Interface CPLD

CDB5376DS612DB3 312.3.6 RS-485 TelemetryBy default, CDB5376 communicates with the PC evaluation software through the microcontroller USBport. Addition

Seite 26 - 26 DS612DB3

CDB537632 DS612DB3A microcontroller software connection is made when the SYNC_MC signal output is created by the micro-controller on command from the

Seite 27 - DS612DB3 27

CDB5376DS612DB3 332.3.8 External ConnectorPower supplies and telemetry signals route to a 20-pin double row connector with 0.1" spacing (J26). Th

Seite 28 - 28 DS612DB3

CDB537634 DS612DB3The VA+ and VA- power supplies to the analog components on CDB5376 can be jumpered to use regu-lated bipolar power supplies (+2.5 V,

Seite 29 - 2.3.5 Phase Locked Loop

CDB5376DS612DB3 35The VD and VCORE power supplies on CDB5376 include reverse-biased Schottkey diodes to ground toprotect against reverse voltages that

Seite 30 - 3.3 V, 10 µA

CDB537636 DS612DB3modulators are 4-wire INR+, INF+, INF-, INR- quad groups, and are routed with INF+ and INF- as a tra-ditional differential pair and

Seite 31 - 2.3.6.1 CLK, SYNC

CDB5376DS612DB3 372.5.4 Dual Row HeadersTo simplify signal tracing on CDB5376, all device pins connect to dual-row headers. These dual-row head-ers ar

Seite 32 - C - SCL, SDA, Bypass

CDB537638 DS612DB33. SOFTWARE DESCRIPTION3.1 Menu BarThe menu bar is always present at the top of the software panels and provides typical File and He

Seite 33 - 2.4 Power Supplies

CDB5376DS612DB3 393.2 About PanelThe About panel displays copyright information for the Cirrus Seismic Evaluation software.Click OK to exit this panel

Seite 34 - 34 DS612DB3

CDB53764 DS612DB33.4.3 Plot Enable ... 493.4.4

Seite 35 - 2.5.2 Differential Pairs

CDB537640 DS612DB33.3 Setup PanelThe Setup panel initializes the evaluation system to perform data acquisition. It consists of the followingsub-panels

Seite 36 - 2.5.3 Bypass Capacitors

CDB5376DS612DB3 413.3.1 USB PortThe USB Port sub-panel sets up the USB communication interface between the PC and the target board.Control Description

Seite 37 - 2.5.4 Dual Row Headers

CDB537642 DS612DB33.3.2 Digital FilterThe Digital Filter sub-panel sets up the digital filter configuration options.By default the Digital Filter sub-

Seite 38 - 3.1 Menu Bar

CDB5376DS612DB3 433.3.3 Analog Front EndThe Analog Front End sub-panel configures the amplifier, modulator, and test DAC pin options. Pin op-tions are

Seite 39 - 3.2 About Panel

CDB537644 DS612DB33.3.5 Gain/OffsetThe Gain / Offset sub-panel controls the digital filter GAIN and OFFSET registers for each channel.The OFFSET and G

Seite 40 - 3.3 Setup Panel

CDB5376DS612DB3 453.3.6 Data CaptureThe Data Capture sub-panel collects samples from the target board and sets analysis parameters.When the Capture bu

Seite 41 - 3.3.1 USB Port

CDB537646 DS612DB33.3.7 External MacrosMacros are generated within the Macros sub-panel on the Control panel. Once a macro has been builtit can either

Seite 42 - 3.3.2 Digital Filter

CDB5376DS612DB3 473.4 Analysis PanelThe Analysis panel is used to display the analysis results on collected data. It consists of the followingcontrols

Seite 43 - 3.3.4 Test Bit Stream

CDB537648 DS612DB33.4.1 Test SelectThe Test Select control sets the type of analysis to be run on the collected data set.Control DescriptionTime Domai

Seite 44 - 3.3.5 Gain/Offset

CDB5376DS612DB3 493.4.2 StatisticsThe Statistics control displays calculated statistics for the selected analysis channel. For multichanneldata captur

Seite 45 - 3.3.6 Data Capture

CDB5376DS612DB3 5LIST OF FIGURESFigure 1. CDB5376 Block Diagram...

Seite 46 - • M2 = . /macros/m2.mac

CDB537650 DS612DB33.4.4 CursorThe Cursor control is used to identify a point on the graph using the mouse and then display its plot values.When any po

Seite 47 - 3.4 Analysis Panel

CDB5376DS612DB3 513.5 Control PanelThe Control panel is used to write and read register settings and to send commands to the digital filter.It consist

Seite 48 - 3.4.1 Test Select

CDB537652 DS612DB33.5.1 DF RegistersThe DF Registers sub-panel writes and reads registers within the digital filter. Digital filter registers con-trol

Seite 49 - 3.4.3 Plot Enable

CDB5376DS612DB3 533.5.4 MacrosThe Macros sub-panel is designed to write a large number of registers with a single command. This al-lows the target eva

Seite 50 - 50 DS612DB3

CDB537654 DS612DB33.5.6 CustomizeThe Customize sub-panel sends commands to upload custom FIR and IIR filter coefficients, upload cus-tom test bit stre

Seite 51 - 3.5 Control Panel

CDB5376DS612DB3 554. BILL OF MATERIALS CIRRUS LOGICCDB5376_REV_D2.bomBILL OF MATERIAL (Page 1 of 3)Item Cirrus P/N Rev Description Qty Reference Desig

Seite 52 - 3.5.3 SPI

CDB537656 DS612DB3CIRRUS LOGICCDB5376_REV_D2.bomBILL OF MATERIAL (Page 2 of 3)Item Cirrus P/N Rev Description Qty Reference Designator MFG MFG P/N Not

Seite 53 - 3.5.5 GPIO

CDB5376DS612DB3 57CIRRUS LOGICCDB5376_REV_D2.bomBILL OF MATERIAL (Page 3 of 3)Item Cirrus P/N Rev Description Qty Reference Designator MFG MFG P/N Not

Seite 54 - 3.5.7 External Macros

CDB537658 DS612DB35. LAYER PLOTS

Seite 56 - 56 DS612DB3

CDB53766 DS612DB3LIST OF TABLESTable 1. Analog Inputs Default Jumper Settings...

Seite 57 - DS612DB3 57

CDB537660 DS612DB3

Seite 58 - 5. LAYER PLOTS

CDB5376DS612DB3 61

Seite 59 - DS612DB3 59

CDB537662 DS612DB3

Seite 60 - 60 DS612DB3

CDB5376DS612DB3 63

Seite 61 - DS612DB3 61

CDB537664 DS612DB3

Seite 62 - 62 DS612DB3

CDB5376DS612DB3 65

Seite 63 - DS612DB3 63

CDB537666 DS612DB36. SCHEMATICS

Seite 64 - 64 DS612DB3

CDB5376DS612DB3 67

Seite 65 - DS612DB3 65

CDB537668 DS612DB3

Seite 66 - 6. SCHEMATICS

CDB5376DS612DB3 69

Seite 67 - DS612DB3 67

CDB5376DS612DB3 71. INITIAL SETUP1.1 Kit ContentsThe CDB5376 evaluation kit includes:• CDB5376 Evaluation Board• USB Cable (A to B)• Software Download

Seite 68 - 68 DS612DB3

CDB537670 DS612DB3

Seite 69 - DS612DB3 69

CDB5376DS612DB3 71

Seite 70 - 70 DS612DB3

CDB537672 DS612DB3

Seite 71 - DS612DB3 71

CDB5376DS612DB3 73

Seite 72 - 72 DS612DB3

CDB537674 DS612DB3

Seite 73 - DS612DB3 73

CDB5376DS612DB3 75

Seite 74 - 74 DS612DB3

CDB537676 DS612DB3

Seite 75 - DS612DB3 75

CDB5376DS612DB3 77

Seite 76 - 76 DS612DB3

CDB537678 DS612DB3

Seite 77 - DS612DB3 77

CDB5376DS612DB3 79

Seite 78 - 78 DS612DB3

CDB53768 DS612DB31.2.1 Default Jumper Settings J27, J227, J327, J427CH1, CH2, CH3, CH4Analog Input SelectionsDAC_OUT+ 1 **2INA+DAC_OUT- 3 **4INA-DAC_

Seite 79 - DS612DB3 79

CDB537680 DS612DB3

Seite 80 - 80 DS612DB3

CDB5376DS612DB3 9 J11VA+ Voltage Selection+2.5VA 1 ---------- 2+5VA 3 **4EXT_VA+ 5 **6 J12VD Input Voltage SourceEXT_VA+ 1 **2EXT_VD 3 ---------- 4J

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