Cirrus-logic CS5560 Bedienungsanleitung

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Preliminary Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 2009
(All Rights Reserved)
http://www.cirrus.com
5/4/09
CS5560
±2.5 V / 5 V, 50 kSps, 24-bit, High-throughput
ΔΣ
ADC
Features & Description
Differential Analog Input
On-chip Buffers for High Input Impedance
Conversion Time = 20 μS
Settles in One Conversion
Linearity Error = 0.0005%
Signal-to-Noise = 110 dB
24 Bits, No Missing Codes
Simple three/four-wire serial interface
Power Supply Configurations:
- Analog: +5 V / GND; IO: +1.8 V to +3.3 V
- Analog: ±2.5 V; IO: +1.8 V to +3.3 V
Power Consumption:
- ADC Input Buffers On: 90 mW
- ADC Input Buffers Off: 60 mW
General Description
The CS5560 is a single-channel, 24-bit analog-to-digital
converter capable of 50 kSps conversion rate. The input
accepts a fully differential analog input signal. On-chip
buffers provide high input impedance for both the AIN in-
puts and the VREF+ input. This significantly reduces the
drive requirements of signal sources and reduces errors
due to source impedances. The CS5560 is a delta-sigma
converter capable of switching multiple input channels at
a high rate with no loss in throughput. The ADC uses a
low-latency digital filter architecture. The filter is designed
for fast settling and settles to full accuracy in one conver-
sion. The converter's 24-bit data output is in serial form,
with the serial port acting as either a master or a slave. The
converter is designed to support bipolar, ground-refer-
enced signals when operated from ±2.5V analog supplies.
The converter can operate from an analog supply of 0-5V
or from ±2.5V. The digital interface supports standard log-
ic operating from 1.8, 2.5, or 3.3 V.
ORDERING INFORMATION:
See Ordering Information on page 32.
AIN+
AIN-
CS
SCLK
SMODE
VREF+
VREF-
RDY
OSC/CLOCK
GENERATOR
CONV
BP/UP
DIGITAL CONTROL
SERIAL
INTERFACE
ADC
DIGITAL
FILTER
LOGIC
VL
MCLK
SDO
RST
SLEEP
VLR
VLR2
V1-
V2-
BUFEN
V2+
V1+
CS5560
TST
DCR
MAY ‘09
DS713PP2
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Inhaltsverzeichnis

Seite 1 - General Description

Preliminary Product InformationThis document contains information for a new product.Cirrus Logic reserves the right to modify this product without not

Seite 2 - TABLE OF CONTENTS

CS556010 DS713PP25/4/09 DIGITAL CHARACTERISTICSTA = TMIN to TMAX; VL = 3.3V, ±5% or VL = 2.5V, ±5% or 1.8V, ±5%; VLR = 0V DIGITAL FILTER CHARACTERIST

Seite 3 - LIST OF TABLES

CS5560DS713PP2 115/4/09GUARANTEED LOGIC LEVELSTA=-40to+85°C;V1+=V2+=+2.5V, ±5%; V1- = V2- = -2.5 V, ±5%;VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±

Seite 4 - ANALOG CHARACTERISTICS T

CS556012 DS713PP25/4/09RECOMMENDED OPERATING CONDITIONS(VLR = 0V, see Note 15)15. The logic supply can be any value VL – VLR = +1.71 to +3.465 volts a

Seite 5 - (CONTINUED) T

CS5560DS713PP2 135/4/092. OVERVIEWThe CS5560 is a 24-bit analog-to-digital converter capable of 50 kSps conversion rate. The device is ca-pable of sw

Seite 6 - SWITCHING CHARACTERISTICS

CS556014 DS713PP25/4/09To perform only one conversion, CONV should return high at least 20 master clock cycles before RDYfalls.Once a conversion is co

Seite 7 - 11. SCLK = MCLK/2

CS5560DS713PP2 155/4/093.2 ClockThe CS5560 can be operated from its internal oscillator or from an external master clock. The state ofMCLK determines

Seite 8 - MSB MSB–1

CS556016 DS713PP25/4/093.4 Analog InputThe analog input of the converter is fully differential with a peak-to-peak input of 4.096 volts on each input

Seite 9

CS5560DS713PP2 175/4/093.6 Typical Connection DiagramsThe following figure depicts the CS5560 powered from bipolar analog supplies, +2.5 V and - 2.5

Seite 10 - DIGITAL CHARACTERISTICS

CS556018 DS713PP25/4/09The following figure depicts the CS5560 device powered from a single 5V analog supply. Figure 7. CS5560 Configured Using a Sin

Seite 11 - GUARANTEED LOGIC LEVELS

CS5560DS713PP2 195/4/093.7 AIN & VREF Sampling StructuresThe CS5560 uses on-chip buffers on the AIN+, AIN-, and the VREF+ inputs. Buffers provide

Seite 12 - ABSOLUTE MAXIMUM RATINGS

CS55602 DS713PP25/4/09TABLE OF CONTENTS1. CHARACTERISTICS AND SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Seite 13 - 3. THEORY OF OPERATION

CS556020 DS713PP25/4/09Figure 9 through Figure 16 illustrate the performance of the converter with various input signal magni-tudes. Frequency (Hz)5

Seite 14 - 14 DS713PP2

CS5560DS713PP2 215/4/09Figure 15 illustrates the device with a small signal 1/1,000,000 of full scale. The signal input for Figure 15is about 8.2 mic

Seite 15 - 3.2 Clock

CS556022 DS713PP25/4/09Figure 17 illustrates the noise floor of the converter from 0.1 Hz to 25 kHz. While the plot does exhibitsome 1/f noise at low

Seite 16 - 3.5 Output Coding Format

CS5560DS713PP2 235/4/093.9 Digital Filter CharacteristicsThe digital filter is designed for fast settling, therefore it exhibits very little in-band

Seite 17 - ±2.5V Analog Supplies

CS556024 DS713PP25/4/093.10 Serial PortThe serial port on the CS5560 can operate in two different modes: synchronous self clock (SSC) mode &synch

Seite 18 - 18 DS713PP2

CS5560DS713PP2 255/4/093.11 Power Supplies & GroundingThe CS5560 can be configured to operate with its analog supply operating from 5V, or with i

Seite 19 - 3.8 Converter Performance

CS556026 DS713PP25/4/093.12 Using the CS5560 in Multiplexing ApplicationsThe CS5560 is a delta-sigma A/D converter. Delta-sigma converters use oversa

Seite 20 - 20 DS713PP2

CS5560DS713PP2 275/4/09At the same time the converter is performing a conversion on a channel from one bank of multiplexers,the second multiplexer ban

Seite 21 - DS713PP2 21

CS556028 DS713PP25/4/094. PIN DESCRIPTIONS CS – Chip Select, Pin 1The Chip Select pin allows an external device to access the serial port. If SMODE =

Seite 22 - 22 DS713PP2

CS5560DS713PP2 295/4/09BP/UP – Bipolar/Unipolar Select, Pin 11The BP/UP pin determines the span and the output coding of the converter. When set high

Seite 23 - Attenuation (dB)

CS5560DS713PP2 35/4/09LIST OF FIGURESFigure 1. SSC Mode - Read Timing, CS remaining low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Seite 24 - 3.10 Serial Port

CS556030 DS713PP25/4/09SCLK – Serial Clock Input/Output, Pin 23The SMODE pin determines whether the SCLK signal is an input or an output signal. SCLK

Seite 25 - DS713PP2 25

CS5560DS713PP2 315/4/095. PACKAGE DIMENSIONSNotes: 1.“D” and “E1” are reference datums and do not included mold flash or protrusions, but do include

Seite 26 - 26 DS713PP2

CS556032 DS713PP25/4/096. ORDERING INFORMATION 7. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION* MSL (Moisture Sensitivity Level) as spec

Seite 27 - DS713PP2 27

CS55604 DS713PP25/4/091. CHARACTERISTICS AND SPECIFICATIONS• Min / Max characteristics and specifications are guaranteed over the specified operating

Seite 28 - 4. PIN DESCRIPTIONS

CS5560DS713PP2 55/4/09ANALOG CHARACTERISTICS (CONTINUED) TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%; VL -VLR = 3.3 V, ±5%;

Seite 29

CS55606 DS713PP25/4/09SWITCHING CHARACTERISTICS TA= -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%;VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%,

Seite 30

CS5560DS713PP2 75/4/09SWITCHING CHARACTERISTICS (CONTINUED) TA= -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%;VL - VLR = 3.3 V, ±5%,

Seite 31 - 24L SSOP PACKAGE DRAWING

CS55608 DS713PP25/4/09SWITCHING CHARACTERISTICS (CONTINUED) TA= -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%;VL - VLR = 3.3 V, ±5%,

Seite 32 - 8. REVISION HISTORY

CS5560DS713PP2 95/4/09SWITCHING CHARACTERISTICS (CONTINUED) TA= -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%;VL - VLR = 3.3 V, ±5%,

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