Cirrus-logic CDB42L52 Bedienungsanleitung

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Copyright © Cirrus Logic, Inc. 2006
(All Rights Reserved)
http://www.cirrus.com
Evaluation Board for CS42L52
Features
Stereo Analog Inputs
4 Stereo Audio Jack Inputs, 2 of which can
be Differential Microphone Inputs
Channel Mixer
MUX’d Analog Output and Speaker Outputs
Headphone/Line Out Jack
Stereo Headphone Jack
Stereo Speaker Outputs w/Banana Jacks
8- to 96-kHz S/PDIF Interface
CS8416 Digital Audio Receiver
CS8406 Digital Audio Transmitter
I/O Stake Headers
External Control Port Accessibility
External DSP Serial Audio I/O Accessibility
Independent, Regulated Power Supplies
1.65 V to 3.3 V Logic Interface
FlexGUI S/W Control - Windows
®
Compatible
Pre-Defined & User-Configurable Scripts
Description
Using the CDB42L52 evaluation board is an ideal way
to evaluate the CS42L52 CODEC. Use of the board re-
quires an analog/digital signal source, an analyzer and
power supplies. A Windows
PC-compatible computer is
also needed in order to configure the CS42L52 and the
board functionality.
System timing can be provided by the CS8416, by the
CS42L52 with supplied master clock, or via an I/O stake
header with a DSP connected.
1/8th inch audio jacks are provided for the CS42L52 an-
alog inputs and HP/Line outputs. Speaker driver
outputs are via Banana jacks. Digital data I/O connec-
tions are via RCA phono or optical connectors to the
CS8416 and CS8406 (S/PDIF Rx and Tx).
The Windows-based software GUI provided makes
configuring the CDB42L52 easy. The software commu-
nicates through the PC’s USB to configure board and
FPGA registers so that all features of the CS42L52 can
be evaluated. The evaluation board may also be con-
figured to accept external timing and data signals for
operation in a user application during system develop-
ment.
ORDERING INFORMATION
CDB42L52 Evaluation Board
Analog Output
(Line + Headphone)
Analog Input
(Line + MIC)
Software Mode
Control Port
CS42L52
S/PDIF Input
(CS8416)
S/PDIF Output
(CS8406)
Clocks/Data
Header
I²C Header
FPGA
Oscillator
(socket)
Reset
MCLK
Reset
Reset
MCLK
Reset
Speaker Outputs
Frequency
Synthesizer PLL
Clk/Data SRC
DECEMBER '06
DS680DB1
CDB42L52
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Inhaltsverzeichnis

Seite 1 - CDB42L52

Copyright © Cirrus Logic, Inc. 2006(All Rights Reserved)http://www.cirrus.comEvaluation Board for CS42L52Features Stereo Analog Inputs– 4 Stereo Audi

Seite 2

10 DS680DB1CDB42L522.4 DSP Engine TabThe “DSP Engine” tab provides high-level control of the SDIN (PCM) data volume level, the ADC out-put/SDIN mix vo

Seite 3 - 1. SYSTEM OVERVIEW

DS680DB1 11CDB42L522.5 Analog and PWM Output Volume TabThe “Analog and PWM Output Volume” tab provides high-level control of the CS42L52 DAC output an

Seite 4

12 DS680DB1CDB42L522.6 Register Maps TabThe Register Maps tabs provide low-level control of the CS42L52, CS8416, CS8406, CS8421, FPGA andGPIO register

Seite 5

DS680DB1 13CDB42L523. SYSTEM CONNECTIONS AND JUMPERS CONNECTOR REF INPUT/OUTPUT SIGNAL PRESENTVP J35 Input +1.6 V to +5.25 V Power Supply. GND J4 I

Seite 6 - 2. SOFTWARE MODE CONTROL

14 DS680DB1CDB42L52 JMP LABEL PURPOSE POSITION FUNCTION SELECTEDJ31 VLSelects source of voltage for the VL supply*+1.8V Voltage source is +1.8 V regul

Seite 7

DS680DB1 15CDB42L52J3 HP/LINEB_R_LOADSelects 32 or 16 ohm load for HP/LINE_OUTB (DAC out)1 - 2 16 ohm load selected. 2 - 3 32 ohm load selected.J9 HP/

Seite 8

16 DS680DB1CDB42L52CDB42L51 BLOCK DIAGRAM Figure 7. Block DiagramAnalog InputsSoftware Mode Control Port CS42L52S/PDIF I/O (CS8406 + CS8416)Clocks/Da

Seite 9

DS680DB1 17CDB42L524. CDB42L51 SCHEMATICSFigure 8. CS42L52 & Analog I/O (Schematic Sheet 1)

Seite 10

18 DS680DB1CDB42L52Figure 9. S/PDIF & Digital Interface (Schematic Sheet 2)

Seite 11

DS680DB1 19CDB42L52Figure 10. Micro & FPGA Control (Schematic Sheet 3)Fi 11

Seite 12

2 DS680DB1CDB42L52TABLE OF CONTENTS1. SYSTEM OVERVIEW ...

Seite 13

20 DS680DB1CDB42L52Figure 11. Power (Schematic Sheet 4)

Seite 14

DS680DB1 21CDB42L525. CDB42L51 LAYOUTFigure 12. Silk Screen

Seite 15

22 DS680DB1CDB42L52Figure 13. Top-Side Layer

Seite 16 - CDB42L51 BLOCK DIAGRAM

DS680DB1 23CDB42L52Figure 14. GND (Layer 2)

Seite 17 - 4. CDB42L51 SCHEMATICS

24 DS680DB1CDB42L52Figure 15. Power (Layer 3)

Seite 18

DS680DB1 25CDB42L52Figure 16. Bottom Side Layer

Seite 19

26 DS680DB1CDB42L526. REVISION HISTORYRevision ChangesDB1 Initial ReleaseContacting Cirrus Logic SupportFor all product questions and inquiries, conta

Seite 20

DS680DB1 3CDB42L521. SYSTEM OVERVIEWThe CDB42L52 platform provides analog and digital interfaces to the CS42L52 and allows for external DSP and I²C® i

Seite 21 - 5. CDB42L51 LAYOUT

4 DS680DB1CDB42L521.5 CS8406 Digital Audio TransmitterA complete description of the CS8406 transmitter (Figure 4 on page 17) and a discussion of the d

Seite 22

DS680DB1 5CDB42L521.9 Analog InputsFour stereo jack connectors supply the AC coupled line-level analog inputs to the CS42L52. Differential orsingle en

Seite 23

6 DS680DB1CDB42L522. SOFTWARE MODE CONTROLThe CDB42L52 may be used with the Microsoft Windows®-based FlexGUI graphical user interface, allowing soft-w

Seite 24

DS680DB1 7CDB42L522.1 Board Configuration TabThe “Board Configuration” tab provides high-level control of signal routing on the CDB42L52. This tab als

Seite 25

8 DS680DB1CDB42L522.2 CODEC Configuration TabThe “CODEC Configuration” tab provides high-level control of the CS42L52 register settings. Status text d

Seite 26 - 6. REVISION HISTORY

DS680DB1 9CDB42L522.3 Analog Input Volume TabThe “Analog Input Volume” tab provides high-level control of all volume settings in the ADC of the CS42L5

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