Cirrus-logic AN364 Bedienungsanleitung

Copyright  Cirrus Logic, Inc. 2012(All Rights Reserved)Cirrus Logic, Inc.http://www.cirrus.comApplication NoteDesign Guide for a CS1610 and CS1611Dim

AN36410 AN364REV3Step 9) Calculate RFBGAIN (R17)Use Equation 12 to calculate the flyback gain resistor, RFBGAIN (R17).whereR17 = RFBGAIN in TTfb = s

AN364AN364REV3 11Step 13) Circuit AdjustmentsCircuit adjustments are required after the transformer has been designed and constructed. Recalculate RFB

AN36412 AN364REV3Notes on Circuit Fine Tuning• Going beyond the RFBGAIN limitation will not have any further effect on the design.• RSense and RFBGAIN

AN364AN364REV3 13Step 15) Determine IPK(BST), ISAT, and RIPK (R13)The boost stage peak current has two distinct values:• IPK(BST) is related to input

AN36414 AN364REV3The AC line current does not follow the inductor peak current envelope because the circuit operates in CRM and DCM. The switching fre

AN364AN364REV3 15The frequency range should be as high as possible without exceeding 75kHz. This strategy will keep the fundamental and second harmoni

AN36416 AN364REV3Step 18) Determine Boost Input CapacitorTo be compatible with a wide range of dimmers, the boost input capacitance should be minimize

AN364AN364REV3 17The BSTAUX pin and FBAUX pin currents must be limited to less than 1mA. A series resistor of at least 22 k must be used to limit the

AN36418 AN364REV3Solving Equation 25 for ‘CODE’:The tracking range of this resistance ADC is approximately 15.5k to 4M. The series resistor RS is us

AN364AN364REV3 19excess charge from capacitor C4 by turning ‘ON’ transistor Q3, dissipating the power into load resistors R6 and R16. The clamp load r

AN3642 AN364REV3Contacting Cirrus Logic SupportFor all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one ne

AN36420 AN364REV34 Design ExampleThe Cirrus Logic CRD1611-8W reference design is used for the design example. The required operating parameters for th

AN364AN364REV3 21Step 5) Determine the Flyback Nominal Timing T1 and T2Use Equation 7 to solve for T1:Use Equation 8 to solve for T2:Step 6) Calculate

AN36422 AN364REV3Using Equation 13, calculate the transformer T1 secondary RMS current:Step 11) Determine Output CapacitorOutput capacitor C5 ripple c

AN364AN364REV3 23Using Equation 20, calculate RIPK:Step 16) Boost Inductor SpecificationsSee Figure 8 in the Boost Inductor Specifications section on

AN36424 AN364REV34.3 Final Design StepsStep 19) Choose Power ComponentsThe drain current through transistor Q4 is limited to 165mA. The smallest 800V

AN364AN364REV3 255 SummaryFigure 11. Schematic600-00543-Z1_Rev_A3JWJWSHEETOFSHEETENGINEERDATEDRAWN BYPART #SHEET4/30/2012SCH.,CRD1611-8W-Z11TITLESIZE

AN36426 AN364REV36 BOARD LAYOUT1 21 2121 2123121212451 23478121212121212Figure 12. PCB Dimensions

AN364AN364REV3 277 Bill of MaterialsFigure 13. Bill of MaterialsCIRRUS LOGICCRD1611-8W_Rev_A.bomBILL OF MATERIALItem Cirrus P/N Rev Description Qty R

AN36428 AN364REV3Revision HistoryRevision Date ChangesREV1 MAR 2012 Initial releaseREV2 JUNE 2012 Corrected typographical errors. REV3 AUG 2012 Contex

AN364AN364REV3 32 IntroductionThis application note is a guide to designing a Solid State Lighting (SSL) LED lamp circuit using Cirrus Logic's CS

AN3644 AN364REV33 Design ProcessThe design process for a two-stage power converter system can be partitioned into six circuit blocks (see Figure 1). T

AN364AN364REV3 53.2 Overview of Design StepsThe CS1610/11 LED driver IC controls a power converter system that has two distinct power conversion stage

AN3646 AN364REV33.3 Flyback Stage DesignFigure 2 illustrates the steps for designing the flyback stage.Figure 2. Flyback Stage DesignFlyback Specific

AN364AN364REV3 7Step 1) Select a Value for Boost Output VoltageThe value of the boost output voltage, VBST, must be greater than the maximum input AC

AN3648 AN364REV3For optimum efficiency, the increase in transformer losses (created by an uneven duty cycle) must balance the reduction of the losses

AN364AN364REV3 9Figure 4 illustrates the switching frequency used in the system design.Solve for T1 and T2 using Equation 7 and Equation 8: Period T1