Cirrus-logic CS4271 Bedienungsanleitung Seite 35
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CS4271
DS592F1 35
6. CONTROL PORT INTERFACE
The Control Port is used to load all the internal settings of the CS4271. The operation of the Control Port may be
completely asynchronous to the audio sample rate. However, to avoid potential interference problems, the Control
Port pins should remain static if no operation is required.
The Control Port has 2 modes: SPI and I²C, with the CS4271 operating as a slave to control messages in both
modes. If I²C operation is desired, AD0/CS
should be tied to VA or AGND. If the CS4271 ever detects a high to low
transition on AD0/CS
after power-up, SPI mode will be selected. The Control Port registers are write-only in SPI
mode.
Upon release of the RST
pin, the CS4271 will wait approximately 10 ms before it begins its start-up sequence. The
part defaults to Stand-Alone Mode, in which all operational modes are controlled as described under “Stand-Alone
Mode” on page 24. The Control Port is active at all times, and if bit 1 of register 07h (CPEN) is set, the part enters
Control-Port Mode and all operational modes are controlled by the Control Port registers. This bit can be set at any
time, but to avoid unpredictable output noises, bit 1 (CPEN) and bit 0 (PDN) of register 07h should be set by writing
03h before the end of the 10 ms start-up wait period. All registers can then be set as desired before releasing the
PDN bit to begin the start-up sequence. If system requirements do not allow writing to the control port immediately
following the release of RST
, the SDIN line should be held at logic “0” until the proper serial mode can be selected.
6.1 SPI Mode
In SPI mode, CS is the CS4271 chip select signal, CCLK is the control port bit clock, CDIN is the input data line from
the microcontroller and the chip address is 0010000. All control signals are inputs and data is clocked in on the rising
edge of CCLK.
Figure 17 shows the operation of the Control Port in SPI mode. To write to a register, bring CS
low. The first 7 bits
on CDIN form the chip address, and must be 0010000. The eighth bit is a read/write indicator (R/W
), which must be
low to write. The next 8 bits form the Memory Address Pointer (MAP), which is set to the address of the register that
is to be updated. The next 8 bits are the data which will be placed into the register designated by the MAP. See
Table 10 on page 36.
The CS4271 has MAP auto increment capability, enabled by the INCR bit in the MAP. If INCR is 0, then the MAP
will stay constant for successive writes. If INCR is set, then MAP will auto increment after each byte is written, al-
lowing block writes to successive registers.
MAP
MSB
LSB
DATA
byte 1
byte n
R/W
MAP = Memory Address Pointer
ADDRESS
CHIP
CDIN
CCLK
CS
0010000
Figure 17. Control Port Timing, SPI mode
- D/A Features 1
- A/D Features 1
- System Features 1
- Ordering Information 2
- Stand-Alone Mode Feature Set 2
- Software Mode Feature Set 2
- General Description 2
- TABLE OF CONTENTS 3
- DS592F1 5 5
- DS592F1 7 7
- HPF enabled 14
- DIGITAL CHARACTERISTICS 17
- 19
- 20 DS592F1 20
- Repeated 21
- 4. TYPICAL CONNECTION DIAGRAM 23
- 5.1.3.2 Clock Ratio Selection 25
- 16-Bit W ord 26
- ½ Bit Dither 26
- 5.2 Control Port Mode 27
- 5.2.3 System Clocking 27
- 5.2.3.2 Clock Ratio Selection 28
- 5.2.5 Dither for 16-Bit Data 30
- 5.2.6 Auto-Mute 30
- 5.2.8 Interpolation Filter 31
- 5.2.9 De-Emphasis 31
- 5.2.10 Oversampling Modes 31
- 5.3 De-Emphasis Filter 31
- 5.4 Analog Connections 32
- 5.4.1 Input Connections 32
- × 6.144 MHz) the digital 32
- 5.4.2 Output Connections 33
- 5.5 Mute Control 34
- 6. CONTROL PORT INTERFACE 35
- 6.1 SPI Mode 35
- I²C Mode 36
- 7. REGISTER QUICK REFERENCE 37
- Function: 38
- 8.5.1 Mute (Bit 7) 42
- 76543210 43
- B7 B6 B5 B4 B3 B2 B1 B0 44
- 9. PARAMETER DEFINITIONS 45
- DS592F1 47 47
- Amplitude (dB) 48
- 52 DS592F1 52
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